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device main/secondary loop maximum frequency package
semiconductor technical data bicmos component for 2 or 3 volt systems ordering information MC145181ftar2 550/60 mhz lqfp32 plastic package case 873c (lqfp32, tape & reel only) verysmall 5 x 5 mm body 32 1 order this document by MC145181/d development system the mc145230evk, which contains hardware and software, is strongly recommended for system development. (the user must provide the vcos for evaluating the MC145181.) the software supports all features and modes of operation of the device. up to four boards or devices can be controlled and the user is alerted to error conditions. the control program may be used with any board based on the MC145181, mc145225, or mc145230. (scale 2:1) 1 motorola rf/if device data 19
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! "! the MC145181 is a dual frequency synthesizer containing verylow supply voltage circuitry. the device supports two independent loops with a single input reference and operates down to 1.8 v. phase noise reduction circuitry is incorporated into the device. the MC145181 operates up to 550 mhz on the main loop and up to 60 mhz on the secondary loop. the device has a 32/33 prescaler for the main loop. lock detection circuitry for both loops is multiplexed to a single output. two 8bit dacs are powered through a dedicated pin. the dac supply range is 1.8 to 3.6 v; this voltage may differ from the main supply. an onchip voltage multiplier supplies power to the phase/frequency detectors. thus, in a 2 v application, the detectors are supplied with 4 v power. in 2.6 to 3.6 v applications, the multiplied voltage is regulated at approximately 5 v. the current source/sink phase/frequency detector for the main loop is designed to achieve faster lock times than a conventional detector. both high and low current outputs are available along with a timer, double buffers, and a mosfet switch to adjust the external lowpass filter response. there are several levels of standby which are controllable with a 1byte transfer through the serial port. either of the plls and/or the reference oscillator may be independently placed in the lowpower standby state. in addition, any of the phase/frequency detector outputs may be placed in the floating state to facilitate modulation of the external vcos. either dac may be placed in standby via a 4byte transfer. the MC145181 facilitates designing the receiver's first and second local oscillators for reflex ? twoway paging applications. also, the device accommodates generation of the transmit carrier. ? operating frequency main loop: 100 to 550 mhz secondary loop: 10 to 60 mhz ? operating supply voltage: 1.8 to 3.6 v ? nominal supply current, both loops active: 3 ma ? maximum standby current, all systems shut down: 10 m a ? phase detector output current: 1.8 v supply e pd out hi: 2.8 ma, pd out lo: 0.7 ma 2.5 v supply e pd out hi: 4.4 ma, pd out lo: 1.1 ma ? two independent 8bit dacs with separate supply pin (up to 3.6 v) ? lock detect output with adjustable lock indication window ? independent r counters allow independent step sizes for each loop ? main loop divider range: 992 to 262,143 ? secondary loop divider range: 7 to 8,191 ? fractional reference counters divider range: 20 to 32,767.5 ? auxiliary reference divider with smallsignal differential output e ratios: 8, 10, 12.5 ? three generalpurpose outputs ? direct interface to motorola spi data port up to 10 mbps reflex and bitgrabber are trademarks of motorola, inc. ? motorola, inc. 1999 rev 1 this document contains information on a new product. specifications and information herein are subject to change without notice. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 2 motorola rf/if device data contents 1. block diagram 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. pin connections 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. parameter tables 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3a. maximum ratings 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3b. dc electrical characteristics 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3c. pd out hi and pd out lo phase/frequency detector characteristics 5 . . . . . . 3d. pd out phase/frequency detector characteristics 5 . . . . . . . . . . . . . . . . . . . . . 3e. dac characteristics 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3f. voltage multiplier and keepalive oscillator characteristics 6 . . . . . . . . . . . . . 3g. dynamic characteristics of digital pins 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3h. dynamic characteristics of loop and f out pins 8 . . . . . . . . . . . . . . . . . . . . . . . . . 4. device overview 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4a. serial interface and registers 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4b. reference input and counters circuits 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4c. loop divider inputs and counter circuits 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4d. voltage multiplier and keepalive circuits 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4e. phase/frequency detectors 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4f. lock detectors 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4g. dacs 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4h. generalpurpose outputs 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. pin descriptions 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5a. digital pins 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5b. reference pins 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5c. loop pins 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5d. analog outputs 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5e. external components 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5f. supply pins 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. detailed register descriptions 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6a. c register 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6b. hr register 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6c. n register 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6d. r register 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6e. hn register 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6f. d register 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. applications information 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7a. crystal oscillator considerations 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7b. main loop filter design e conventional 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7c. main loop filter design e adapt 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7d. secondary loop filter design 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7e. voltage multiplier stall avoidance 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. programmer's guide 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8a. quick reference 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8b. initializing the device 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8c. programming without adapt 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8d. programming utilizing horseshoe with adapt 66 . . . . . . . . . . . . . . . . . . . . . . . . . . 8e. controlling the dacs 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9. application circuit 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10. outline dimensions 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 3 motorola rf/if device data clk f in enb c register 8 bits output a mux output c output a pd out hi 16 9 19 power connections: pin 2 = dac v pos pins 11, 24, 26, and 29 = v pos pins 14, 15, 18, and 31 = gnd output b 25 d in phase / frequency detector, timer, and control f in out c out b/ref out a function high current charge pump timer ph det pulse f r f r pll stby pll stby pd float pd float osc stby low current charge pump n register 24 bits n counter 18 stages 3 f v r counter 16 stages f r 16 r register 16 bits 16 hr register 16 bits 3 r register 24 bits 16 r counter 16 stages n counter 13 stages 13 n register 13 bits 13 msbs hn register 16 bits d register 16 bits shift register and address generator 5 6 7 18 + 12 13 amp loi gain polarity pll stby oscillator osc e osc b 1 32 rx 17 pd out lo 20 lock detector voltage multiplier and regulator c mult 21 c reg 22 ld 8 lock detector window vmult control phase / frequency detector f v f r pd out 23 supply current minimization circuit 2 2 test polarity ratio 10 mode f in 30 amp 8 8 auxiliary divider 3 stages f out /pol 28 f out /pol 27 dac 8 bits dac1 3 dac 8 bits dac2 4 dac v pos 2 1. block diagram osc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 4 motorola rf/if device data 2. pin connections output a this device contains 15,260 active transistors. v pos 25 32 31 30 29 28 27 26 24 23 22 21 20 19 18 17 output b v pos f out / pol f out / pol v pos f in gnd osc b pd out c reg c mult pd out lo pd out hi gnd rx 16 output c 15 gnd 14 gnd 13 f in 12 f in 11 v pos 10 mode 9 1 2 3 4 5 6 7 8 osc e dac v pos dac1 dac2 enb d in clk ld 3. parameter tables 3a. maximum ratings (voltages referenced to gnd, unless otherwise stated) parameter symbol value unit dc supply voltages v pos , dac v pos 0.5 to 3.6 v dc input voltage e osc e , f in , f in , mode, d in , clk, enb , f out /pol , f out /pol v in 0.5 to v pos + 0.5 v dc output voltage v out 0.5 to v pos + 0.5 v dc input current, per pin i in 10 ma dc output current, per pin i out 20 ma dc supply current, v pos and gnd pins i 25 ma power dissipation, per package p d 100 mw storage temperature t stg 65 to 150 c lead temperature, 1 mm from case for 10 seconds t l 260 c notes: 1. maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin descriptions section. 2. esd (electrostatic discharge) immunity meets human body model (hbm) up to 2000 v. additional esd data available upon request. this device contains protection circuitry to guard against damage due to high static volt- ages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 5 motorola rf/if device data 3b. dc electrical characteristics v pos = 1.8 to 3.6 v, voltages referenced to gnd, t a = 40 to 85 c, unless otherwise statedtt parameter condition symbol guaranteed limit unit maximum lowlevel input voltage (d in , clk, enb , mode, f out /pol , f out /pol) f out /pol and f out /pol configured as inputs v il 0.3 x v pos v minimum highlevel input voltage (d in , clk, enb , mode, f out /pol , f out /pol) f out /pol and f out /pol configured as inputs v ih 0.7 x v pos v minimum hysteresis voltage (clk) v hys 100 mv maximum lowlevel output voltage (ld, output a, output b) i out = 20 m a v ol 0.1 v minimum highlevel output voltage (ld, output a, output b) i out = 20 m a v oh v pos 0.1 v minimum lowlevel output current (ld, output a, output b) v out = 0.3 v i ol 0.7 ma minimum highlevel output current (ld, output a, output b) v out = v pos 0.3 v i oh 0.7 ma minimum lowlevel output current (output c) v out = 0.2 v i ol 2.8 ma maximum input leakage current (d in , clk, enb , mode, f out /pol , f out /pol) v in = v pos or gnd; f out /pol and f out /pol configured as inputs i in 1.0 m a maximum output leakage current (output b, output c) v out = v pos or gnd; output in highimpedance state i oz 1 m a maximum on resistance (output c) 1.8 v v pos < 2.5 v supply 2.5 v v pos 3.6 v supply (note 1) r on 75 50 w maximum standby supply current (v pos and dac v pos tied together) v in = v pos or gnd; outputs open; both plls in standby mode; oscillator in standby mode; dac1 and dac2 output = zero; keepalive oscillator off (notes 2, 3, and 4) i stby 10 m a notes: 1. for supply voltages restricted to 2.5 to 2.9 v and an ambient temperature range of 10 to 60 c, output c has a guaranteed on resistance range of 23 to 44 w. 2. the total supply current drain for the keepalive oscillator, voltage multiplier, and regulator is approximately 250 m a. 3. when the mode pin is tied high, bit c6 must be programmed to a 0 for minimum supply current drain. otherwise, if c6 = 1, the current drain is approximately 8 m a for a 1.8 v supply and approximately 40 m a for a 3.6 v supply. this restriction on bit c6 does not apply when the mode pin is tied low. 4. to ensure minimum standby supply current drain, the voltage potential at the c mult pin must not be allowed to fall below the potential at the v pos pins. see discussion in section 5e under c mult . 3c. pd out hi and pd out lo phase/frequency detector characteristics nominal output current, v pos = 1.8 v: pd out hi = 2.8 ma, pd out lo = 0.7 or 0.35 ma nominal output current, v pos 2.5 v: pd out hi = 4.4 ma, pd out lo = 1.1 or 0.55 ma rx = 2.0 k w , voltages referenced to gnd, voltage multiplier on, t a = 40 to 85 c parameter condition guaranteed limit unit maximum source current variation parttopart (see note) v out = 0.5 x v cmult 14 % maximum sinkversussource mismatch (see note) v out = 0.5 x v cmult 20 % output voltage range (see note) i out variation 27% 0.6 to v cmult 0.6 v v maximum threestate leakage current v out = 0 or v cmult 50 na note: percentages calculated using the following formula: (maximum value minimum value) / maximum value. 3d. pd out phase/frequency detector characteristics v pos = 1.8 to 3.6 v, voltages referenced to gnd, voltage multiplier on, t a = 40 to 85 c parameter condition guaranteed limit unit minimum lowlevel output current v out = 0.3 v 0.3 ma minimum highlevel output current v out = v cmult 0.3 v 0.3 ma maximum threestate leakage current v out = 0 or v cmult 50 na f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 6 motorola rf/if device data 3e. dac characteristics v pos = 1.8 to 3.6 v, dac v pos = 1.8 to 3.6 v; t a = 40 to 85 c parameter condition guaranteed limit unit resolution 8 bits maximum integral nonlinearity 1 lsb maximum offset voltage from gnd no external load 1 lsb maximum offset voltage from dac v pos no external load 2 lsb maximum output impedance over entire output range, including zero output (which is lowpower standby) 130 k w maximum standby current zero output, no external load (see i stby in section 3b) maximum supply current per dac @ dac v pos pin except with zero output, no external load (dac v pos ) / 36 ma 3f. voltage multiplier and keepalive oscillator characteristics voltages referenced to gnd, t a = 40 to 85 c parameter condition guaranteed limit unit voltage multiplier output voltage 5 mhz refresh rate, 100 m a continuous sourcing, measured at c mult pin v pos = 1.8 v v pos = 3.6 v 3.32 to 3.78 4.75 to 5.35 v keepalive refresh frequency v pos = 1.8 to 3.6 v 300 to 700 khz 3g. dynamic characteristics of digital pins v pos = 1.8 to 3.6 v, t a = 40 to 85 c, input t r = t f = 10 ns, c l = 25 pf parameter figure no. symbol guaranteed limit unit serial data clk frequency note: refer to clk t w below 1 f clk dc to 10 mhz maximum propagation delay, enb to output a (selected as generalpurpose output) 2, 7 t plh , t phl 200 ns maximum propagation delay, enb to output b 2, 3, 7, 8 t plh , t phl , t pzl , t plz , t pzh , t phz 200 ns maximum propagation delay, enb to output c 4, 8 t pzl , t plz 200 ns maximum output transition time, output a; output b with active pullup and pulldown 2, 7 t tlh , t thl 75 ns minimum setup and hold times, d in versus clk 5 t su , t h 30 ns minimum setup, hold, and recovery times, enb versus clk 6 t su , t h , t rec 100 ns minimum pulse width, inactive (high) time, enb 6 t w * cycles minimum pulse width, clk 1 t w 50 ns maximum input capacitance e d in , clk, enb c in 10 pf * for hr register access, the minimum limit is 20 osc e cycles. for hn register access, the minimum limit is 27 f in cycles. for n register access, the minimum limit is 20 osc e cycles + 99 f in cycles. when the timer is used for adapt, the minimum limit after the second n register access and before the next register access is the timeout interval + 99 f in cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 7 motorola rf/if device data figure 1. figure 2. 10% v pos gnd 1/f clk clk 90% 90% 50% 10% t plh t phl t tlh t thl t w t w t f t r enb output a output b v pos gnd 50% d in clk 50% valid 50% t su t h v pos gnd v pos gnd figure 3. clk enb 50% t su t h first clock last clock t rec 50% v pos gnd v pos gnd t w figure 4. test point device under test c l * * includes all probe and fixture capacitance. test point device under test c l * * includes all probe and fixture capacitance. 250 m a figure 5. figure 6. figure 7. figure 8. enb t pzl t plz t phz 10% 90% high impedance enb output c output c v pos gnd t pzl 50% t plz 10% 90% high impedance source current and limit voltage to v pos for t plz and t pzl . sink current and limit voltage to gnd for t phz and t pzh . v pos gnd 50% output b output b output b output b 90% 10% t pzh f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 8 motorola rf/if device data 3h. dynamic characteristics of loop and f out pins v pos = 1.8 to 3.6 v, t a = 40 to 85 c symbol parameter condition figure no. min max unit v in input voltage range, f in 100 mhz f in < 550 mhz 9 100 300 mvpp v in input voltage range, f in 10 mhz f in < 60 mhz 10 100 400 mvpp f osce input frequency range, osc e v in = 350 to 600 mvpp, device in external reference mode 11 9 80 mhz f xtal crystal frequency, osc b and osc e device in crystal mode * 9 80 mhz c in input capacitance of pins osc b and osc e e e pf f out output frequency range, f out and f out output signal swing > 300 mvpp per pin (600 mvpp differential) 12 1 6.2 mhz f f operating frequency range of the phase/frequency detectors, pd out hi, pd out lo, pd out dc 600 khz * refer to the crystal oscillator considerations section. figure 9. figure 10. rf meter r l = 50 w 100 pf device under test v pos v pos f in gnd f in 100 pf 100 pf device under test v pos v pos f in v in gnd v in rf meter r l = 50 w sine wave generator z out = 50 w sine wave generator z out = 50 w sine wave generator device under test v pos v pos osc e v in 50 w figure 11. gnd osc b device under test f out figure 12. no connection 0.1 m f f out 20 pf 20 pf v v peaktopeak voltage measurement f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 9 motorola rf/if device data 4. device overview refer to the block diagram in section 1. 4a. serial interface and registers the serial interface is comprised of a clock pin (clk), a data in pin (d in ), and an enable pin (enb ). information on the data input pin is shifted into a shift register on the lowtohigh transition of the serial clock. the data format is most significant bit (msb) first. both clk and enb are schmitttriggered inputs. the r and n registers contain counter divide ratios for the main loop, pll. the r and n registers contain counter divide ratios for the secondary loop, pll . additional contol bits are located in the r , n, and c registers. the d register controls the digitaltoanalog converters (dacs). random access is allowed to the n, r , hr, hn , d, and c registers. two 16bit holding registers, hr and hn , feed registers r and n , respectively. [the three least significant bits (lsbs) of the hn register are not used.] the r and n registers determine the divide ratios of the r and n counters, respectively. thus, the information presented to the r and n counters is doublebuffered. using the proper programming sequence, new divide ratios may be presented to the n, r, and n counters; simultaneously. enb is used to activate the data port and allow transfer of data. to ensure that data is accepted by the device, the enb signal line must initially be a high voltage (not asserted), then make a transition to a low voltage (asserted) prior to the occurrence of a serial clock, and must remain asserted until after the last serial clock of the burst. serial data may be transferred in an spi format (while enb remains asserted). data is transferred to the appropriate register on the rising edge of enb (see table 1). ashort shiftingo, depicted as bitgrabber ? in the table, allows access to certain registers without requiring address bits. when enb is inactive (high), clk is inhibited from shifting the shift register. the serial input pins may not be driven above the supply voltage applied to the v pos pins. 4b. reference input and counters circuits reference (oscillator) circuit for the colpitts reference oscillator, one pin ties to the base (osc b , pin 32) and the other ties to the emitter (osc e , pin 1), of an onchip npn transistor. in addition, the reference circuit may be operated in the external reference (xref) mode as selectable via bit c6 when the mode pin is high. the osc b and osc e pins support an external fundamental or overtone crystal. the output of the oscillator is routed to both the reference counter for the main loop (r counter) and the reference counter for the secondary loop (r counter). in a second mode, determined by bit c6 being 1 and the mode pin being high, osc e is an input which accepts an accoupled signal from a tcxo or other source. osc b must be floated. if the mode pin is low, this axref modeo is not allowed. reference counter for main loop main reference counter r divides down the frequency at osc e and feeds the phase/frequency detector for the main loop. the detector feeds the two charge pumps with outputs pd out hi and pd out lo. the division ratio of the r counter is determined by bits in the r register. reference counter for secondary loop secondary reference counter r divides down the frequency at osc e and feeds the phase/frequency detector for the secondary loop. the detector output is pd out . the division ratio of the r counter is determined by the 16 lsbs of the r register. the r counter has a special mode to provide a frequency output at pins f out and f out (differential outputs). these are lowjitter ecltype outputs. with the mode pin low, software control allows the osc e frequency to be dividedby8, 10, or 12.5 and routed to the f out pins. this output is derived by tapping off of a frontend stage of the r counter and feeding the auxiliary counter which provides the divideddown frequency. the chip must have the mode pin low, which activates the f out pins. the actual r divide ratio must be divisible by 2 or 2.5 when the f out pins are activated. there is no such restriction when the mode pin is high. see section 6d, r register. 4c. loop divider inputs and counter circuits f in inputs and counter circuit f in and f in are highfrequency inputs to the amplifier which feeds the n counter. a small signal can feed these inputs either differentially or singleended. the n counter divides down the external vco frequency for the main loop. (the divide ratio of the n counter is also known as the loop multiplying factor.) the divide ratio of this counter is determined by the 18 lsbs of the n register. the output of the n counter feeds the phase/frequency detector for the main loop. f in input and counter circuit f in is the highfrequency input to the amplifier which feeds the n counter. a small signal can feed this input singleended. the n counter divides down the external vco frequency for the secondary loop. (the divide ratio of the n counter is also known as the loop multiplying factor.) the divide ratio of this counter is determined by bits in the n register. the output of the n counter feeds the phase/frequency detector for the secondary loop. 4d. voltage multiplier and keepalive circuits the voltage multiplier produces approximately two times the voltage present at the v pos pins over a supply range of 1.8 v to about 2.5 v. with a supply range of approximately 2.5 v to 3.6 v, the elevated voltage is regulated/limited to approximately 5 v. the elevated voltage, present at the c mult f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 10 motorola rf/if device data pin, is applied to both phase detectors. an external capacitor to gnd is required on the c mult pin. the other capacitors required for the multiplier are onchip. a capacitor to gnd is also required on the c reg pin. the voltage on this pin is equal to the voltage on the v pos pins over a supply range of 1.8 v to about 2.5 v. the voltage on c reg is limited to approximately 2.5 v maximum when the v pos pins exceed 2.5 v. the refresh rate determines the repetition rate that the capacitors for the voltage multiplier are charged. refresh is normally derived off of the signal present at the osc e pin, through a divider which is part of the voltage multiplier and regulator circuitry. the refresh rate is controlled via bits in the r register. when the reference oscillator circuit is placed in standby, an onchip keepalive oscillator assists in maintaining the elevated voltage on the phase detectors. the keepalive refresh rate is per the spec table in section 3f. if desired, the keepalive oscillator can be inhibited from turning on, by placing the multiplier in the inactive state via r register bits. this causes the phase/frequency detector voltage to bleed off while in standby, but has the advantage of achieving the lowest supply current if all other sections of the chip are shut down. 4e. phase/frequency detectors detector for main loop the detector for the main loop senses the phase and frequency difference between the outputs of the r and n counters. the detector feeds both a highcurrent charge pump with output pd out hi and a lowcurrent charge pump with output pd out lo. the charge pumps can be operated in three conventional manners as controlled by bits in the n register. pd out lo can be enabled with pd out hi inhibited. conversely, pd out hi can be enabled with pd out lo inhibited. both outputs can be enabled and tied together externally for maximum charge pump current. finally, both outputs can be inhibited. in this last case, they float. the outputs can also be forced to the floating state by a bit in the c register. this facilitates introduction of modulation into the vco input. the charge pumps can be operated in an adapt mode as controlled by bits in the n register. the bits essentially program a timer which determines how long pd out hi is active. after the timeout, pd out hi floats and pd out lo becomes active. in addition, a second set of r and n counter values can be engaged after the timeout. for more information, see table 16 and section 8, programmer's guide . detector for secondary loop the detector for the secondary loop senses the phase and frequency difference between the outputs of the r and n counters. detector output pd out is a voltagetype output with a threestate pushpull driver. the output can be forced to the floating state by a bit in the c register. this facilitates introduction of modulation into the vco input. 4f. lock detectors window counters in each of the lock detector circuits determine the lock detector phase threshold for pll and pll . the window counter divide ratio for the main loop's lock detector is controlled via a bit in the n register. the window counter divide ratio for the secondary loop is not controllable by the user. the lock detector window determines a minimum phase difference which must occur before the lock detect pin goes high. note that the lock detect signals for each loop drive an and gate, which then feeds the ld pin. the ld pin indicates the condition of both loops, or the one active loop if the other is in standby. if both loops are in standby, ld is low indicating unlocked. 4g. dacs the two independent 8bit dacs facilitate crystal oscillator trimming and pa output power control. they are also suitable for any generalpurpose use. each dac utilizes an r2r ladder architecture. the output pins, dac1 and dac2, are directly connected to the ladder; that is, there is no onchip buffer. the dac outputs are determined by the contents of the d register. when a dac output is zero scale, it is also in a lowpower mode. the poweron reset (por) circuit initializes the dacs in the lowpower mode upon power up. 4h. generalpurpose outputs there are three outputs which may be used as port expanders for a microcontroller unit (mcu). output a is actually a multipurpose output with a pushpull output driver. see table 2 for details. output b is a threestate output. the state of output b depends on two bits; one of these bits also controls whether the main pll is in standby or not. see table 5 for details. output c is an opendrain output. the state of this output is controlled by one bit per table 4. output c is specified with a guaranteed on resistance, and thus, may be used in an analog fashion. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 11 motorola rf/if device data 5. pin descriptions 5a. digital pins enb , d in , and clk pins 5, 6, and 7 e serial data port inputs the enb input is used to activate the serial interface to allow the transfer of data to the device. to transfer data to the device, the enb pin must be low during the interval that the data is being clocked in. when enb is taken back high (inactive), data is transferred to the appropriate register depending either on the data stream length or address bits. the c, hr, and n registers can be accessed using either a unique data stream length (bitgrabber) or by using address bits (conventional). the d, hn , and r registers can only be accessed using address bits. see table 1. the bit stream begins with the msb and is shifted in on the lowtohigh transition of clk. the bit pattern is 1 byte (8 bits) long to access the c register, 2 bytes (16 bits) to access the hr register, or 3 bytes (24 bits) to access the n register. a bit pattern of 4 bytes (32 bits) is used to access the registers when using address bits. the device has double buffers for storage of the n and r counter divide ratios. one double buffer is composed of the hr register which feeds the r register. an hr to r register transfer occurs whenever the n register is written. the other double buffer is the hn register which feeds the n register. an hn to n register transfer occurs whenever the n register is written. thus, new divide ratios may be presented to the r, n , and n counters simultaneously. transitions on enb must not be attempted while clk is high. this puts the device out of synchronization with the microcontroller. resynchronization occurs whenever enb is high (inactive) and clk is low. data is retained in the registers over a supply range of 1.8 to 3.6 v. the bitstream formats are shown in figures 13 through 18. ld pin 8 e lock detectors output this signal is the logical and of the lock detect signals from both pll and pll . for the main pll, the phase window that defines alocko is programmable via bit n22. the phase window for the secondary pll is not programmable. if either pll or pll is in standby, ld indicates the lock condition of the active loop only. if both loops are in standby, the ld output is a static low level. each pll's lock detector is in the high state when the respective loop is locked (the inputs to the phase detector being the same phase and frequency). the lock detect signal is in the low state when a loop is out of lock. see figure 19. upon power up, the ld pin indicates a not locked condition. the ld pin is a pushpull cmos output. if unused, ld should be left open. output a pin 9 e multiplepurpose digital output depending on control bits r 21 and r 20, output a is selectable by the user as a generalpurpose output (either high or low level), f r (output of main reference counter), f r (output of secondary reference counter), or a phase detector pulse indicator for both loops. when selected as generalpurpose output, bit c7 determines whether the output is a high or low level per table 2. when configured as f r , f r , or phase detector pulse, output a appears as a normally low signal and pulses high. output a is a slewrate limited cmos totempole output. if unused, output a should be left open. table 1. register access (lsbs are c0, r0, n0, d0, r 0, and n 0) access type accessed register address nibble number of clocks register bit nomenclature figure no. bitgrabber c e 8 c7, c6, c5, ..., c0 13 bitgrabber hr e 16 r15, r14, r13, ..., r0 14 bitgrabber n e 24 n23, n22, n21, ..., n0 15 conventional c $0 32 c7, c6, c5, ..., c0 13 conventional hr $1 32 r15, r14, r13, ..., r0 14 conventional n $2 32 n23, n22, n21, ..., n0 15 conventional d $3 32 d15, d14, d13, ..., d0 18 conventional r $5 32 r 23, r 22, r 21, ..., r 0 16 conventional hn $4 32 n 15, n 14, n 13, ..., n 0 17 note: $0 denotes hexadecimal zero, $1 denotes hexadecimal one, etc. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 12 motorola rf/if device data table 2. output a configuration bit r 21 bit r 20 bit c7 function of output a 0 0 0 generalpurpose output, low level 0 0 1 generalpurpose output, high level 0 1 x f r 1 0 x f r 1 1 x phase detector pulse indicator mode pin 10 e mode input when the mode pin is tied low (approximately gnd), the pair of pins named f out /pol and f out /pol become outputs f out and f out . as such, these pins are the divided down reference frequency. the division ratio is controlled by bits per table 6. in addition, when mode is low, the r counter is preceded by a fixeddivide prescaler. also, only a crystal may be used at pins osc b and osc e ; an external reference, such as a tcxo, should not be used to drive either pin. the default on the phase detector polarity is positive. see the summary in table 3. when the mode pin is tied high (approximately v pos ), the pair of pins named f out /pol and f out /pol become inputs pol and pol. as such, these pins control the polarity of the phase/frequency detectors for pll and pll, respectively. in addition, when mode is high, the r counter is preceded by a dualmodulus prescaler. therefore, the r counter is completely programmable per figure 16. also, either a crystal or tcxo may be used with the device. see the summary in table 3. table 3. mode pin summary attribute mode pin = low level mode pin = high level f out /pol pin pin is f out output; polarity of phase detector is positive pin is pol input and controls polarity of phase detector f out /pol pin pin is f out output; polarity of phase detector is positive pin is pol input and controls polarity of phase detector oscillator circuit supports a crystal only supports crystal or accommodates tcxo r counter programmable in increments of 2 or 2.5 programmable in increments of 0.5 output b pin state of pin controlled by bit c6 pin not used, bit c6 controls whether crystal or tcxo is accommodated output c pin 16 e generalpurpose digital output this pin is controllable by bit c5 as either low level or high impedance per table 4. the output driver is an opendrain nchannel mosfet connected to gnd. the esd (electrostatic discharge) protection circuit for this pin is tied to gnd and v pos . thus, voltages above v pos are clipped at approximately 0.7 v above v pos . if unused, output c should be left open. table 4. output c programming bit c5 state of output c pin 0 low level (on resistance per electrical table) 1 high impedance (leakage per electrical table) output b pin 25 e generalpurpose digital output this pin is controllable by bits c6 and c1 as either low level, high level, or high impedance per table 5. note that whenever the main pll is placed in standby by bit c1, output b is forced to high impedance. the threestate mosfet output is slewrate limited. if unused, output b should be left open. table 5. output b programming bit c6 bit c1 state of output b pin condition of main pll 0 0 low level active 0 1 high impedance* standby* 1 0 high level active 1 1 high impedance standby *powerup default. f out /pol and f out /pol pins 28 and 27 e dualpurpose outputs/inputs these pins are outputs when the mode pin is low and inputs when the mode pin is high. when the mode pin is low, these pins are smallsignal differential outputs f out and f out with a frequency derived from the signal present at the osc e pin. the frequency of the output signal is per table 6. if this function is not needed, the mode pin should be tied high, which minimizes supply current. in this case, these inputs must be tied high or low per tables 7 and 8. table 6. f out and f out frequency (mode pin = low) bit n23 bit r 1 bit r 0 output frequency 0 0 0 osc e divided by 10 0 0 1 osc e divided by 12.5 0 1 0 osc e divided by 12.5 0 1 1 osc e divided by 12.5 1 0 0 osc e divided by 8 1 0 1 osc e divided by 10 1 1 0 osc e divided by 10 1 1 1 osc e divided by 10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 13 motorola rf/if device data when the mode pin is high, these pins are digital inputs pol and pol which control the polarity of the phase/frequency detectors. see tables 7 and 8. positive polarity is used when an increase in an external vco control voltage input causes an increase in vco output frequency. negative polarity is used when a decrease in an external vco control voltage input causes an increase in vco output frequency. table 7. main phase/frequency detector polarity (mode pin = high) mode pin pol pin main detector polarity (pd out lo and pd out hi) high low positive high high negative low * positive *pin configured as an output; should not be driven. table 8. secondary phase/frequency detector polarity (mode pin = high) mode pin pol pin secondary detector polarity (pd out ) high low positive high high negative low * positive *pin configured as an output; should not be driven. 5b. reference pins osc e and osc b pins 1 and 32 e reference oscillator transistor emitter and base these pins can be configured to support an external crystal in a colpitts oscillator configuration. the required connections for the crystal circuit are shown in the crystal oscillator considerations section. additionally, the pins can be configured to accept an external reference frequency source, such as a tcxo. in this case, the reference signal is ac coupled into osc e and the osc b pin is left floating. see figure 11. bit c6 and the mode input pin control the configuration of these pins per table 9. table 9. reference configuration mode input pin bit c6 reference configuration comment low x supports crystal (default) c6 used to control output b* high 0 supports crystal output b not useful high 1 requires external reference output b not useful *see table 5. 5c. loop pins f in and f in pins 12 and 13 e frequency input for main loop (pll) these pins feed the onchip rf amplifier which drives the highspeed n counter. this input may be fed differentially. however, it is usually used in a singleended configuration with f in driven while f in is tied to a good rf ground (via a capacitor). the signal source driving this input must be ac coupled and originates from an external vco. the sensitivity of the rf amplifier is dependent on frequency as shown in the loop specifications table. sensitivity of the f in input is specified as a level across a 50 w load driven by a 50 w source. a vco that can drive a load within the data sheet limits can also drive f in . usually, to avoid load pull and resultant frequency modulation of the vco, f in is lightly coupled by a small value capacitor and/or a resistor. see the applications circuit of figure 65. f in pin 30 e frequency input for secondary loop (pll ) this pin feeds the onchip rf amplifier which drives the highspeed n counter. this input is used in a singleended configuration. the signal source driving this input must be ac coupled and originates from an external vco. the sensitivity of the rf amplifier is dependent on frequency as shown in the loop specifications table. sensitivity of the f in input is specified as a level across a 50 w load driven by a 50 w source. a vco that can drive a load within the data sheet limits can also drive f in . usually, to avoid load pull and resultant frequency modulation of the vco, f in is lightly coupled by a small value capacitor and/or a resistor. see the applications circuit of figure 65. if the secondary loop is not used, pll should be placed in standby and f in should be left open. pd out hi and pd out lo pins 19 and 20 e phase/frequency detector outputs for main loop (pll) each pin is a threestate current source/sink/float output for use as a loop error signal when combined with an external lowpass loop filter. under bit control, pd out lo has either onequarter or oneeighth the output current of pd out hi per table 10. the detector is characterized by a linear transfer function (no dead zone). the polarity of the detector is controllable. the operation of the detector is described below and shown in figure 20. table 10. current ratio of pd out hi and pd out lo bit n18 output current ratio pd out hi:pd out lo (gain ratio) 0 4 : 1 1 8 : 1 when the mode pin is high, positive polarity occurs when the pol pin is low. also, when the mode pin is low, polarity f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 14 motorola rf/if device data defaults to positive. positive polarity is described below. f v is the output of the main loop's vco divider (n counter). f r is the output of the main loop's reference divider (r counter). (a) frequency of f v > f r or phase of f v leading f r : currentsinking pulses from a floating state. (b) frequency of f v < f r or phase of f v lagging f r : currentsourcing pulses from a floating state. (c) frequency and phase of f v = f r : essentially a floating state, voltage at pin determined by loop filter. when the mode pin is high, negative polarity occurs when the pol pin is high. negative polarity is described below. f v is the output of the main loop's vco divider (n counter). f r is the output of the main loop's reference divider (r counter). (a) frequency of f v > f r or phase of f v leading f r : currentsourcing pulses from a floating state. (b) frequency of f v < f r or phase of f v lagging f r : currentsinking pulses from a floating state. (c) frequency and phase of f v = f r : essentially a floating state, voltage at pin determined by loop filter. these outputs can be enabled and disabled by bits in the c and n registers. placing the main pll in standby (bit c1 = 1) forces the detector outputs to a floating state. in addition, setting the pd float bit (bit c4 = 1) forces the detector outputs to a floating state while allowing the counters to run for the main pll. for selection of the outputs, see table 11. the phase detector gain (in amps per radian) = pd out current (in amps) divided by 2 p . if a detector output is not used, that pin should be left open. table 11. selection of main detector outputs bit n21 bit n20 bit n19 result 0 0 0 both outputs not enabled 0 0 1 pd out lo enabled 0 1 0 pd out hi enabled 0 1 1 both pd out lo and pd out hi enabled 1 0 0 pd out hi enabled for 16 f r cycles only, then pd out lo enabled 1 0 1 pd out hi enabled for 32 f r cycles only, then pd out lo enabled 1 1 0 pd out hi enabled for 64 f r cycles only, then pd out lo enabled 1 1 1 pd out hi enabled for 128 f r cycles only, then pd out lo enabled notes: 1. when a detector output is not enabled, it is floating. 2. setting bit n21 = 1 places the ic in an adapt mode and engages a timer. pd out pin 23 e phase/frequency detector output for secondary loop (pll ) this pin is a threestate voltage output for use as a loop error signal when combined with an external lowpass loop filter. the detector is characterized by a linear transfer function (no dead zone). the polarity of the detector is controllable. the operation of the detector is described below and shown in figure 21. when the mode pin is high, positive polarity occurs when the pol pin is low. also, when the mode pin is low, polarity defaults to positive. positive polarity is described below. f v is the output of the secondary loop's vco divider (n counter). f r is the output of the secondary loop's reference divider (r counter.) (a) frequency of f v > f r or phase of f v leading f r : negative pulses from high impedance. (b) frequency of f v < f r or phase of f v lagging f r : positive pulses from high impedance. (c) frequency and phase of f v = f r : essentially a highimpedance state, voltage at pin determined by loop filter. when the mode pin is high, negative polarity occurs when the pol pin is high. negative polarity is described below. f v is the output of the secondary loop's vco divider (n counter). f r is the output of the secondary loop's reference counter (r counter.) (a) frequency of f v > f r or phase of f v leading f r : positive pulses from high impedance. (b) frequency of f v < f r or phase of f v lagging f r : negative pulses from high impedance. (c) frequency and phase of f v = f r : essentially a highimpedance state, voltage at pin determined by loop filter. this output can be enabled and disabled by bits in the c register. placing the secondary pll in standby (bit c0 = 1) forces the detector output to a highimpedance state. in addition, setting the pd float bit (bit c3 = 1) forces the detector output to a highimpedance state while allowing the counters to run for pll . the phase detector gain (in volts per radian) = c mult voltage (in volts) divided by 4 p . if the secondary loop is not used, pll should be placed in standby and pd out should be left open. 5d. analog outputs dac1 and dac2 pins 3 and 4 e digitaltoanalog converter outputs these are independent outputs of the two 8bit d/a converters. the output voltage is determined by bits in the d register. each output is a static level with an output impedance of approximately 100 k w . the dacs may be used for crystal oscillator trimming, pa (power amplifier) output power control, or other generalpurpose use. if a dac output is not used, the pin should be left open. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 15 motorola rf/if device data 5e. external components rx pin 17 e currentsetting resistor an external resistor to gnd at this pin sets a reference current that is used to determine the current at the phase/frequency detector outputs pd out hi and pd out lo. a value of 2 k w is required. c mult pin 21 e voltagemultiplier capacitor an external capacitor to gnd at this pin is used for the onchip voltage multiplier circuit. the value of this capacitor must be greater than 20 times the value of the largest loop filter capacitor. for example, if the largest loop filter capacitor on either the main loop or the secondary loop is 0.01 m f, then a 0.22 m f capacitor could be used on the c mult pin. to ensure minimum standby supply current drain, the voltage potential at the c mult pin must not be allowed to fall below the potential at the v pos pins. therefore, if the keepalive oscillator is shut off, the user should tie a large value resistor (> 10 m w ) between the c mult pin and v pos . this resistor should be sized to overcome leakage from c mult to gnd due to the printed circuit board and the external capacitor. the consequence of not using the resistor is higher supply current drain in standby. if standby is not used, the resistor is not necessary. also, if the keepalive oscillator is used, the resistor can be omitted. c reg pin 22 e regulator capacitor an external capacitor to gnd at this pin is required for the onchip voltage regulator. a value of 1 m f is recommended. 5f. supply pins dac v pos pin 2 e positive supply potential for dacs this pin supplies power to both dacs and determines the fullscale output of the dacs. the fullscale output is approximately equal to the voltage at dac v pos . the voltage applied to this pin may be more, less, or equal to the potential applied to the v pos pins. the voltage range for dac v pos is 1.8 to 3.6 v with respect to the gnd pins. if both dacs are not used, dac v pos should be tied to the same potential as v pos . v pos pins 11, 24, 26, and 29 e principal positive supply potential these pins supply power to the main portion of the chip. all v pos pins must be at the same voltage potential. the voltage range for v pos is 1.8 to 3.6 v with respect to the gnd pins. for optimum performance, all v pos pins should be tied together and bypassed to a ground plane using a lowinductance capacitor mounted very close to the device. lead lengths and printed circuit board traces between the capacitor and the ic package should be minimized. (the veryfast switching speed of the device can cause excessive current spikes on the power leads if they are improperly bypassed.) gnd pins 14, 15, 18, and 31 e ground common ground for the device. all gnd pins must be at the same potential and should be tied to a ground plane. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 16 motorola rf/if device data figure 13. enb clk d in a3 a2 a1 a0 c7 c6 c5 c4 c3 c2 c1 c0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 xxxx xxxx xxx xx xxxx xxx 0 enb clk d in 12345678 c7 c6 c5 c4 c3 c2 c1 c0 notes: 1. to access the c register, either 8 or 32 clock cycles can be used. 2. for the 8bit stream, no address bits are needed. 3. for the 32bit stream, address bits a3 through a0 are required. 4. at this point, the new byte is transferred to the c register. no other register is affected. 5. x signifies a don't care bit. note 4 note 4 6. detailed register descriptions 6a. c register 0 0 0 figure 13. c register access and formats f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 17 motorola rf/if device data c register bits see figure 13 for c register access and serial data formats. out a (c7) when the output a pin is selected as a generalpurpose output (via bits r 21 = r 20 = 0), bit c7 determines the state of the pin. when c7 is 1, output a is forced to a high level. when c0 is 0 output a is forced low. when output a is not selected as a generalpurpose output, bit c7 has no function; i.e., c7 is a adon't careo bit. out b/xref (c6) bit c6 is a dualpurpose bit. when the mode pin is tied low, c6 and c1 (pll stby), can be used to control output b. see table 12. (the reference circuit defaults to crystal configuration.) when the mode pin is tied high, additional control of the reference circuit is allowed. see table 13. table 12. out b/xref bit with mode pin = low bit c6 bit c1 state of output b pin condition of main pll 0 0 low level active 0* 1* high impedance* standby* 1 0 high level active 1 1 high impedance standby *power up default. table 13. out b/xref bit with mode pin = high bit c6 reference configuration 0* supports crystal* 1 accommodates external reference *power up default. out c (c5) this bit determines the state of the output c pin. when c5 is 1, output c is forced to a highimpedance state. when c5 is 0, output c is forced low. pd float (c4) this bit controls the phase detector for the main loop, outputs pd out hi and pd out lo. when this bit is 0, the main phase detector operates normally. when the bit is 1, the outputs are forced to the floating state which opens the loop and allows modulation to be introduced into the external vco input. during this time, the counters are still active. this bit is inhibited from affecting the phase detector during a pd out hi or pd out lo pulse. if the loop is locked prior to c4 being set to 1, the lock detect signal from the main loop continues to indicate alocko immediately after pd float is set to 1. if the phase of the loop drifts outside the lock detect window, then the lock detect signal indicates anot lockedo. if the loop is not locked, and pd float is set to 1, then the lock detect signal from the main loop continues to indicate anot lockedo. pd float (c3) this bit controls the phase/frequency detector for the secondary loop, output pd out . when this bit is 0, the secondary phase detector operates normally. when the bit is 1, the output is forced to the floating state which opens the loop and allows modulation to be introduced into the external vco input. during this time, the counters are still active. this bit is inhibited from affecting the phase detector during a pd out pulse. if the loop is locked prior to c3 being set to 1, the lock detect signal from the secondary loop continues to indicate alocko immediately after pd float is set to 1. if the phase of the loop drifts outside the lock detect window, then the lock detect signal indicates anot lockedo. if the loop is not locked, and pd float is set to 1, then the lock detect signal from the secondary loop continues to indicate anot lockedo. osc stby (c2) this bit controls the crystal oscillator and external reference input circuit. when this bit is 0, the circuit is active. when the bit is 1, the circuit is shut down and is in the lowpower standby mode. when this circuit is shut down, a keepalive oscillator for the voltage doubler is activated, unless the doubler is shut off via bits in the r register. in the crystal oscillator mode, when c2 transitions from a 1 to a 0 state, a kickstart circuit is engaged for a few milliseconds. the kickstart circuit ensures selfstarting for a properlydesigned crystal oscillator note whenever c2 is 1, both bits c1 and c0 must be 1, also. to minimize standby supply current, the voltage multiplier may be shut down (by bits r 19, r 18, and r 17 being all zeroes). if this is the case and the voltage multiplier feature is being used, the user must allow sufficient time for the phase/frequency detector supply voltage to pump up when the multiplier is brought out of standby. this apump upo time is dependent on the c mult capacitor size. pump current is approximately 100 m a. during the pump up time, either the pll standby bits c1 and c2 must be 1 or the phase/ frequency detector float bits c3 and c4 must be 1. pll stby (c1) when set to 1, this bit places the main pll in the standby mode for reduced power consumption. pd out hi and pd out lo are forced to the floating state, the n and r counters are inhibited from counting, the main loop's input amp is shut off, the rx current is inhibited, and the main phase/frequency detector is shut off. the reference oscillator circuit is still active and independently controlled by bit c2. when this bit is programmed to 0, the main pll is taken out of standby in two steps. first, the input amplifier is activated, all counters are enabled, and the rx current is no longer inhibited. any f r and f v signals are inhibited from toggling the phase/frequency detectors and lock detector at this time. second, when the f r pulse occurs, the n counter is loaded, and the phase/frequency and lock detectors are initialized via both flipflops being reset. immediately after the load, the n and r counters begin counting down together. at this point, the f r and f v pulses are enabled to the phase f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 18 motorola rf/if device data and lock detectors, and the phase/frequency detector output is enabled to issue an error correction pulse on the next f r and f v pulses. (patent issued on this method.) during standby, data is retained in all registers and any register may be accessed. when setting or clearing the pll stby bit, other bits in the c register may be changed simultaneously. pll stby (c0) when set to 1, this bit places the pll section of the chip, which includes the onchip f in input amp, in the standby mode for reduced power consumption. pd out is forced to the floating state. the r and n counters are inhibited from counting and placed in the lowcurrent mode. the exception is the r counter's prescaler when the mode pin is low. the r counter's prescaler remains active along with the f out and f out pins when pll is placed in standby (mode pin = low). when the mode pin is low, the f out pin, f out pin, and r counter's prescaler are shut down only when osc stby bit c2 is set to 1. when c0 is reset to 0, pll is taken out of standby in two steps. all pll counters and the input amp are enabled. any f r and f v signals are inhibited from toggling the associated phase/frequency detector at this time. second, when the f r pulse occurs, the n counter is loaded and the phase/ frequency detector is initialized via both flipflops being reset. immediately after the load, the n and r counters begin counting down together. at this point, the f r and f v pulses are enabled to the phase and lock detectors, and the phase/frequency detector output is enabled to issue an error correction pulse on the next f r and f v pulses. (patent issued on this method.) during standby, data is retained in all registers, and any register may be accessed. when setting or clearing the pll stby bit, other bits in the c register may be changed simultaneously. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 19 motorola rf/if device data figure 14. 6b. hr register enb clk d in a3 a2 a1 a0 r7 r6 r5 r4 r3 r2 r1 r0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 x x x x x x x x x x x x r15 r14 r13 r12 r11 r10 r9 r8 0 enb clk d in 12345678 r15 r14 r13 r12 r11 r10 r9 r8 1. to access the hr register (the holding register or first buffer of the doublebuffered hr and 2. for the 16bit stream, no address bits are needed. 3. for the 32bit stream, address bits a3 through a0 are required. 4. at this point, the two new bytes are transferred to the hr register. therefore, the r counter 5. a transfer from hr (holding) register to the r register occurs with each n register access. note 4 note 4 6. x signifies a don't care bit. 910 111213141516 r7 r6 r5 r4 r3 r2 r1 r0 see below see below see below see below 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 0 1 6 7 8 9 a b not allowed not allowed not allowed r counter ratio = 20.5 r counter ratio = 21 r counter ratio = 21.5 . . . f f . . . f f . . . e f r counter ratio = 32,767 r counter ratio = 32,767.5 hexadecimal 0 0 0 0 0 0 0 0 . . . f f decimal (note 7) not allowed . . . . . . . . . . . . r counter ratio = 20 0 2 c r counter ratio = 22 0 001 r combination), either 16 or 32 clock cycles can be used. divide ratio is not altered yet and retains the previous ratio loaded. no other register is affected. 7. the decimal value multiplied by 2 = the hexadecimal value. notes: figure 14. hr register access and formats f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 20 motorola rf/if device data figure 15. 6c. n register enb clk d in a3 a2 a1 a0 n7 n6 n5 n4 n3 n2 n1 n0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 x x x x n23 n22 n21 n20 n19 n18 n17 n16 n15 n14 n13 n12 n11 n10 n9 n8 0 enb clk d in 12345678 1. to access the n register, either 24 or 32 clock cycles can be used. 2. for the 24bit stream, no address bits are needed. 3. for the 32bit stream, address bits a3 through a0 are required. note 4 note 4 910 111213141516 see below see below see below see below 0 0 0 0 0 0 0 0 0 0 3 3 3 3 3 3 0 1 e f 0 1 2 3 not allowed not allowed not allowed . . . f f . . . f f . . . e f hexadecimal 0 0 0 0 0 0 0 0 . . . 1 1 decimal not allowed . . . . . . . . . . . . 03 4 0 010 4. at this point, the three new bytes are transferred to the n register. in addition, an hr to r and hn' to n' transfer occurs. 5. x signifies a don't care bit. 0 0 d d e e e e f f e . . . . . . 0 0 0 0 0 0 0 0 1 1 0 . . . . . . binary current ratio ld window control phase detector program 17 18 19 20 21 22 23 24 n7 n6 n5 n4 n3 n2 n1 n0 n23 n22 n21 n20 n19 n18 n17 n16 n15 n14 n13 n12 n11 n10 n9 n8 see below see below n counter ratio = 992 n counter ratio = 993 n counter ratio = 994 n counter ratio = 995 n counter ratio = 996 n counter ratio = 262,142 n counter ratio = 262,143 notes: figure 15. n register access and formats f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 21 motorola rf/if device data n register bits see figure 15 for n register access and serial data formats. control (n23) when the mode pin is low, control bit n23 determines the divide ratio of the auxiliary divider which feeds the buffers for the f out and f out pins. see table 14 for the overall ratio between osc e and f out /f out . when the mode pin is high, n23 must be programmed to 1. table 14. osc e to f out frequency ratio, mode = low n23 r 1 r 0 osc e to f out frequency ratio 0 0 0 10:1 0 0 1 12.5:1 0 1 0 12.5:1 0 1 1 12.5:1 1 0 0 8:1 1 0 1 10:1 1 1 0 10:1 1 1 1 10:1 ld window (n22) bit n22 determines the lock detect window for the main loop. refer to table 15 and figure 19. table 15. lock detect window n22 ld window (approximated) 0 32 osc e periods 1 128 osc e periods phase detector program (n21, n20, n19) these bits control which phase detector outputs are active for the main loop. these bits also control the timer interval when adapt is utilized for the main loop. see table 16. table 16. main phase detector control n21 n20 n19 result 0 0 0 both pd out hi and pd out lo floating 0 0 1 pd out hi floating, pd out lo enabled 0 1 0 pd out hi enabled, pd out lo floating 0 1 1 both pd out hi and pd out lo enabled 1 0 0 pd out hi enabled and pd out lo floating for 16 f r cycles, then pd out hi floating and pd out lo enabled 1 0 1 pd out hi enabled and pd out lo floating for 32 f r cycles, then pd out hi floating and pd out lo enabled 1 1 0 pd out hi enabled and pd out lo floating for 64 f r cycles, then pd out hi floating and pd out lo enabled 1 1 1 pd out hi enabled and pd out lo floating for 128 f r cycles, then pd out hi floating and pd out lo enabled current ratio (n18) this bit allows for mcu control of the pd out hi to pd out lo current (or gain) ratio on the main loop phase/frequency detector outputs. see table 17. table 17. pd out hi to pd out lo current ratio n18 pd out hi to pd out lo current ratio pd out hi current c mult pin = 5 v (nominal) pd out lo current c mult pin = 5 v (nominal) 0 4:1 4.4 ma 1.1 ma 1 8:1 4.4 ma 0.55 ma n counter divide ratio (n17 to n0) these bits control the n counter divide ratio or loop multiplying factor. the minimum allowed value is 992. the maximum value is 262,143. for ease of programming, binary representation is used. for example, if a divide ratio of 1000 is needed, the 1000 in decimal is converted to binary 00 0000 0011 1110 1000 and is loaded into the device for n17 to n0. see figure 15. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 22 motorola rf/if device data figure 16. 6d. r register enb clk d in a3 a2 a1 a0 r'7 r'6 r'5 r'4 r'3 r'2 r'1 r'0 1 2 3 4 5 6 7 8 910 11121314151617181920 212223242526 272829303132 x x x x r'23 r'22 r'21 r'20 r'19 r'18 r'17 r'16 r'15 r'14 r'13 r'12 r'11 r'10 r'9 r'8 0 note 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 6 7 8 9 a b not allowed not allowed not allowed . . . f f . . . f f . . . e f hexadecimal . . . decimal (note 4) not allowed . . . . . . . . . . . . 00 c 101 5. x signifies a don't care bit. 0 0 2 2 2 2 2 2 f f 2 output a function y vmult control r' counter ratio = 20 r' counter ratio = 20.5 r' counter ratio = 21 r' counter ratio = 21.5 r' counter ratio = 22 r' counter ratio = 32,767 r' counter ratio = 32,767.5 coefficient tst/rst (user must program to 0) 1. to access the r' register, 32 clock cycles must be used. 2. address bits a3 through a0 are required. 3. at this point, the three new bytes are transferred to the r' register. no other register is affected. 4. the decimal value multiplied by 2 = the hexadecimal value. counter divide ratios shown apply when the mode pin is tied high. for ratios when the mode pin is tied low, see table 21. notes: figure 16. r' register access and format f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 23 motorola rf/if device data r register bits see figure 16 for r register access and serial data format. y coefficient (r 23 and r 22) these bits are programmed per table 18. note that for the MC145181, the bits are always programmed as 0 0. for compatibility, the other combinations are reserved for use with the mc145225 and mc145230. table 18. y coefficient r 23 r 22 maximum allowed frequency at f in pin 0 0 550 mhz 0 1 (not used) 1 0 (not used) 1 1 (not used) output a function (r 21 and r 20) these bits control the function of the output a pin per table 19. when selected as a generalpurpose output, bit c7 controls the state of the pin. the signals f r and f r are the outputs of the r and r counters, respectively. the selection as a detector pulse is a test feature. table 19. output a function selection r 21 r 20 function selected for output a 0 0 generalpurpose output 0 1 f r 1 0 f r 1 1 phase/frequency detector pulse from either loop vmult control (r 19, r 18, r 17) these bits control the voltage multiplier per table 20. when the multiplier is in the active state, the bits determine the voltage multiplier's refresh rate of the capacitor tied to the c mult pin. when active, the bits should be programmed for the lowest possible maximum frequency shown in the table. this ensures that the voltage multiplier is operating at optimum efficiency. for example, for a system utilizing a 16.8 mhz reference, bits r 19, r 18, and r 17 should be programmed as 0 0 1 if the user desires to use the voltage multiplier. if the user does not want to use the multiplier, the bits should be programmed as 0 0 0. in the latter case, only a 0.1 m f bypass capacitor is needed at the c mult pin and an external phase/frequency detector supply voltage of 3.6 to 5.25 v must be provided to the c mult pin. table 20. voltage multiplier control r 19 r 18 r 17 multiplier state maximum allowed frequency at osc e pin 0 0 0 inactive 80 mhz 0 0 1 active 20 mhz 0 1 0 active 40 mhz 0 1 1 active 80 mhz 1 x x e (for factory evaluation) test/rst (r 16) this bit must be programmed to 0 by the user. r counter divide ratio (r 15 to r 0) these bits control the r counter divide ratio. thus, these bits determine the secondary loop's minimum step size. this step size is the same as the phase/frequency detector's operating frequency which must not exceed 600 khz. with the mode pin tied high, the minimum allowed value is 20. the maximum value is 32,767.5. for ease of programming, binary representation is used. however, the binary value must be multiplied by 2. for example, if a divide ratio of 1000 is needed, the 1000 in decimal is converted to binary 0000 0011 1110 1000. this value is multiplied by 2 and becomes 0000 0111 1101 0000 and is loaded into the device for r 15 to r 0. see figure 16. with the mode pin tied low, table 21 shows the divide ratios available. there are two formulas for the divide ratio when mode is low. if r 1 r 0 are 0 0: r ratio = (value of r 15 to r 2) x 2. if r 1 r 0 are 0 1, 1 0, 1 1: r ratio = (value of r 15 to r 2) x 2.5. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 24 motorola rf/if device data table 21. r counter divide ratios with mode pin tied low* r 15 r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 r counter divide ratio 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 not allowed 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 not allowed 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 not allowed 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 20 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 25 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 x 25 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 22 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 27.5 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 x 27.5 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 24 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 30 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 x 30 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 26 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 32.5 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 x 32.5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 32,766 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 40,957.5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x 40,957.5 * divide ratios with the mode pin tied high are shown in figure 16. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 25 motorola rf/if device data figure 17. 6e. hn register enb clk d in a3 a2 a1 a0 n'7 n'6 n'5 n'4 n'3 n'2 n'1 n'0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 x x x x x x x x x x x x n'15 n'14 n'13 n'12 n'11 n'10 n'9 n'8 0 note 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 6 7 8 9 a b not allowed not allowed not allowed . . . f f . . . f f . . . e f hexadecimal . . . decimal (note 6) not allowed . . . . . . . . . . . . 00 c 100 5. x signifies a don't care bit. 0 0 9 9 9 9 9 9 f f 9 6. the decimal value multiplied by 8 = the hexadecimal value. 1. to access the hn' register (the holding register or first buffer of the doublebuffered hn' and n' combination), 32 clock cycles must be used. 2. address bits a3 through a0 are required. 3. at this point, the two new bytes are transferred to the hn' register. therefore, the n' counter divide ratio is not altered yet and retains the previous ratio loaded. no other register is affected. 4. a transfer from the hn' (holding) register to the n' register occurs with each n register access. n' counter ratio = 19 n' counter ratio = 20 n' counter ratio = 21 n' counter ratio = 22 n' counter ratio = 23 n' counter ratio = 8,190 n' counter ratio = 8,191 figure 17. hn' register access and format notes: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 26 motorola rf/if device data notes: figure 18. 6f. d register enb clk d in a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 x x x x x x x x x x x x d15 d14 d13 d12 d11 d10 d9 d8 0 note 3 0 1 2 3 d e hexadecimal 0 0 0 0 f f decimal f f 01 1 . . . . . . dac1 dac2 5. x signifies a don't care bit. 1. to access the d register, 32 clock cycles are used. 2. address bits a3 through a0 are required. 3. at this point, the two new bytes are transferred to the d register. no other register is affected. 4. lowpower standby state. zero + 1 lsb output, v = (dac v ) (1/256) out pos zero + 2 lsb output, v = (dac v ) (2/256) out pos zero output, v = (dac v ) (0/256) (note 4) out pos zero + 3 lsb output, v = (dac v ) (3/256) out pos full scale output, v = (dac v ) (255/256) out pos 0 1 2 3 d e hexadecimal 0 0 0 0 f f decimal f f . . . . . . zero + 1 lsb output, v = (dac v ) (1/256) out pos zero + 2 lsb output, v = (dac v ) (2/256) out pos zero output, v = (dac v ) (0/256) (note 4) out pos zero + 3 lsb output, v = (dac v ) (3/256) out pos full scale output, v = (dac v ) (255/256) out pos figure 18. d register access and format full scale 2 lsb output, v = (dac v ) (253/256) out pos full scale 1 lsb output, v = (dac v ) (254/256) out pos full scale 2 lsb output, v = (dac v ) (253/256) out pos full scale 1 lsb output, v = (dac v ) (254/256) out pos f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 27 motorola rf/if device data figure 19. lock detector operation f r vs f v phase relationship ld output one f r period > ld window < ld window < ld window < ld window < ld window < ld window < ld window > ld window > ld window locked unlocked notes: 1. illustration shown is for the main loop and applies when the secondary loop is either phase locked or in standby. the actual detector outputs for each loop are anded together at the ld pin. 2. the secondary loop is similar to the above illustration. 3. the approximate lock detect window for the main loop is either 64 or 256 osc e cycles and is programmable via bit n22. the approximate window for the secondary loop is 64 osc e cycles and is not programmable. 4. the ld output is low whenever the phase difference is more than the lock detect window. 5. the ld output is high whenever the phase difference is less than the lock detect window and continues to be less than the window for 3 f r periods or more. lock detector output conditions f r versus f v relation lock detector output microcontroller action frequency is the same with phase inside the ld window static high level output senses high level and no edges, therefore loop is locked frequency is the same with phase outside the ld window static low level output senses low level, therefore loop is unlocked frequency is slightly different, thus phase is changing dynamic achatteringo output, output has transitions senses edges, therefore loop is unlocked frequency is grossly different static low level output senses low level, therefore loop is unlocked note: for simplicity, this table applies to the main loop. the secondary loop is similar. the detector outputs feed an and gate whose output is the ld pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 28 motorola rf/if device data figure 20. pd out hi and pd out lo detector output characteristics *at this point, when both f r and f v are in phase, the output source and sink circuits are turned on for a short interval. notes: 1. the detector generates error pulses during outoflock conditions. when locked in phase and frequency, the output is high impedance and the voltage at that pin is determined by the lowpass filter capacitor. 2. waveform shown applies when the f out / pol pin is low and the mode pin is high. 3. when the f out / pol pin is high and mode is high, the pd out hi and pd out lo waveform is inverted. 4. the waveform shown is also the default when the mode pin is low. f r reference osc e r) f v vco feedback (f in n) pd out hi, pd out lo source current float sink current * figure 21. pd out detector output characteristics *at this point, when both f r and f v are in phase, the output source and sink circuits are turned on for a short interval. notes: 1. the detector generates error pulses during outoflock conditions. when locked in phase and frequency, the output is high impedance and the voltage at that pin is determined by the lowpass filter capacitor. 2. waveform shown applies when the f out / pol pin is low and the mode pin is high. 3. when the f out / pol pin is high and mode is high, the pd out waveform is inverted. 4. the waveform shown is also the default when the mode pin is low. f r reference osc e r ) f v vco feedback (f in n ) pd out high voltage high z low voltage * f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 29 motorola rf/if device data 7. applications information 7a. crystal oscillator considerations the oscillator/reference circuit may be connected to operate in either of two configurations. with the mode pin placed ahigho and bit c6 programmed to 1, the oscillator/reference circuit of the MC145181 will accept an external reference input. the external reference signal should be capacitive, connected to osc e with osc b left floating. commercially available temperature compensated crystal oscillators (tcxos) or crystalcontrolled data clock oscillators provide a very stable reference frequency. for additional information about tcxos and data clock oscillators, please consult the electronic engineers master catalog, internet web page, or similar publication/service. the onchip colpitts reference oscillator can be selected by either tying the mode pin low or by programming the c6 bit to zero when mode is high. the oscillator may be operated in either the fundamental mode, as show by figure 22, or as an overtone oscillator. the akick starto feature ensures reduced astallingo of hardstarting crystals. crystal resonators the equivalent circuit of a crystal resonator most commonly used is shown in figure 23. the crystal itself is a specially cut (usually at for overtone operation) block of quartz. the dimensions, (shape, thickness, length, and width) determine the operating characteristics of the crystal. when deformed and allowed to return naturally to its resting shape, it is observed to oscillate. this oscillation has the typical characteristics of a damped oscillation and an equivalent electrical signal can be found on the surface of the crystal. in addition, if an equivalent electrical signal is applied to the crystal, it will be observed to oscillate. the equivalent values for r s , l s , c s , and c o can be used to predict the operation of the crystal when used as an electronic oscillator. due to the series/parallel arrangement of the equivalent components, the crystal exhibits two resonances. the first, sometimes just called resonance, is the series resonance of the r s , c s , l s branch. the other, sometimes called the antiresonance, is the parallel resonance including c o . for the series resonance the formula is f s = 2 p l s c s 1 . for parallel resonance, the formula is f p = 2 p 1 l s c s c o c o + c s . as can be seen from this equation, the antiresonant frequency is higher than the series resonant frequency. the ratio between the resonant and antiresonant frequency can be found using the formula c s = d f f 2 (c o + c s ) where d f = ? f s f p and . 2 f s + f p f = by exploiting this characteristic, the crystal oscillator frequency can be tuned slightly. if a capacitor is connected in series with the crystal operating in the resonance mode, the frequency will shift upward. if a capacitance is added in parallel with a crystal operating in an antiresonant mode, the frequency will be shifted down. figure 22. fundamental mode oscillator circuit 0 x 1 0 0 c3 c2 c1 r1 r2 q1 m1 +v osc b osc e frequency synthesizer i1 200/800 m a m2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 30 motorola rf/if device data 2 1 2 1 2 1 r s l s c s r e x e c o x 1 figure 23. crystal resonator equivalent circuit note: values are supplied by crystal manufacturer (parallel resonant crystal). figure 24. overtone crystal equivalent circuit 2 1 l1 s c1 s r1 s c o l3 s c3 s r3 s l5 s c5 s r5 s because of the acoustic properties of the crystal resonator, the crystal atanko responds to energy not only at its fundamental frequency, but also at specific multiples of the fundamental frequency. in the same manner that a shorted or open transmission line responds to multiples of the fundamental frequency, the crystal atanko responds similarly. a shorted halfwave transmission line (or closed acoustic chamber) will not only resonate at its fundamental frequency, but also at odd multiples of the fundamental. these are called the overtones of the crystal and represent frequencies at which the crystal can be made to oscillate. the equivalent circuit of an overtone crystal is shown is figure 24. the components for the appropriate overtone are represented by 1, 3, and 5. the fundamental components are represented by 1, and those of importance for the third and fifth overtones, by 3 and 5. fundamental mode the equivalent circuit for the colpitts oscillator operating in the fundamental mode is shown in figure 25. c3 is selected to provide a small reduction in the inductive property of the crystal. in this manner, the frequency of the oscillator can be apulledo slightly. the biasing combination of m1r1 and m2r2 provide the ability to start operation with a higher than normal operating current to stimulate crystal activity. this akick starto current is nominally four times the normal current. an internal counter times the application of the akick starto and returns the current to normal after the time out period. the mutual conductance (transconductance) of the transistor q1 is useful in determining the conditions necessary for oscillation. the nominal value for the transconductance is found from the formula i e gm = 26 where ie is the emitter current in ma. the operation of the oscillator can be described using the concept of anegative resistanceo. in a normal tuned circuit, any excitation tends to be dissipated by the resistance of the circuit and oscillation dies out. the resistive part of the crystal along with the resistance of the wiring and the internal resistance of c1, c2, and c3, make up this adampingo resistance. some form of energy must be fed back into the circuit to sustain oscillation. this is the purpose of the amplifier. figure 25. fundamental mode colpitts oscillator equivalent circuit 0 0 c3 c2 c1 r1 r2 q1 m1 +v osc b osc e frequency synthesizer i1 200/800 m a 0 r1 s c o c1 s r st m2 l1 s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 31 motorola rf/if device data if we define the damping as resistive, we can define the opposite or regenerative property as negative resistance. figure 26 shows the basic circuit of the colpitts oscillator. c3 has been combined with the crystal elements for simplicity. for the circuit to oscillate, there must be at least as much anegative resistanceo (regeneration) as there is resistance (damping). we can define this by deriving the input impedance for the amplifier. figure 26. colpitts oscillator basic circuit q1 c2 c1 i in v in if a driving signal is defined as v in , the resultant current that flows can be identified as i in . the relationship of v in to i in is v in = i in (z c1 + z c2 ) i b (z c2 b z c1 ) and 0 = i in (z c2 ) + i b (z c2 + r b ) where i b is the base current of transistor q1. solving the two equations and assuming z c2 << r b , the input impedance can be expressed as z in j w 1 c1 c2 c1 + c2 gm w 2 c1 c2 + where w = 2 p f. this is equivalent to the series combination of a real part whose value is real = gm w 2 c1 c2 and the imaginary part whose value is imag = j w 1 c1 c2 c1 + c2 to sustain oscillation, the amplifier must generate a anegative resistanceo equal or greater than the real part of the above equation and opposite in polarity. r neg = gm w 2 c1 c2 as long as the relation r neg = sum (r s + r st + r c1 + r c2 + r c3 ) , the circuit will oscillate and the frequency of oscillation will be defined as f o = 2 p l s (c1 || c2 || c3) 1 where c3 is the series frequency adjusting capacitor. in determining values for c1, c2, and c3, two limits are considered. at one end is the relationship of c3 to c2 and c1. if c3 is made 0 or the reactance of c3 is small compared to the reactance of c1 and c2, no adjustment of the crystal frequency is possible. the other limit is the relationship gm z c1 z c2 > r sum where r sum is the sum of resistances in the resonant loop. since this equation must be true for the circuit to oscillate, it is obvious that as the values of c1 and c2 are increased, the series resistances must be reduced and/or gm increased. since gm is a function of device current and there is a physical limit on how small r sum can be made, at some point oscillation can no longer be sustained. normally, it is desirable to choose the anegative resistanceo to be several times greater than the adampingo resistance to ensure stable operation. a factor of four or five is a good arule of thumbo choice. to determine crystal power, the equivalent circuit shown in figure 27 can be used. in this case, we are addressing a condition where the transistor amplifier is operating at the limit of class a; that is, the device is just at cutoff during the peak negative excursions. at this point, r e = gm x c1 x c2 if the amplitude is constant and the oscillator is stable. for this to occur, the sum of all resistances in the resonant loop will be equal to r e , where r e represents the effective resistance of i1. this can be written as r sum = r s + r st = r e where r s is the crystal resistance and r st is the additional distributed resistances within the resonant loop. at the point where the transistor enters cutoff we have the equation (i in i b ) z c2 + (i in + b ib ) z c1 = v1 + v2 x ls + r e x ls + r e i in = . b = current gain of the transistor. rewriting: i b (z c2 b z c1 ) z c1 + z c2 + x ls + r e i in = . for oscillation to occur, we must have z c1 + z c2 + x ls 0 . if we assume b z c1 is normally much greater than z c2 then i in i e z c1 r e . for the condition we have specified, i e (bias) + i e (instantaneous ac) = 0 the transistor is just cutting off and the peak current, i in is equal to the bias current. the peak input current is represented as i in (peak) = i e |z c1 | r e . the power dissipation of the series resistances in the resonant loop can be written as (i e |z c1 |) 2 = i in (peak) 2 r 2 2 r sum p = where r sum = r e . the power dissipation for the crystal itself becomes (i e |z c1 |) 2 2 r s p crystal = . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 32 motorola rf/if device data figure 27. equivalent circuit for crystal power estimation c2 c1 r s r e 200/800 m a x 1 i1 b lb l b l s v cc x r2 / (r1 + r2) r1 || r2 i in v cc overtone operation for overtone operation, the circuit is modified by the addition of an inductor, l1; and a series capacitor, c4. c4 is inserted as a dc blocking capacitor whose capacitance is chosen sufficiently large so that its reactance can be ignored. this circuit is shown in figure 28. for oscillation to occur at the overtone frequency, the condition gm z c1 z c2 > r s must exist. z c1 represents the impedance across c1 and can be defined as z c1 = jx c1 || (r l1 + jx l1 ) where r l1 is the dc resistance of the inductor l1. for overtone operation, this must occur at the desired harmonic. for example, if the crystal is chosen to oscillate at the third overtone, c1 and c2 must be chosen so that the above condition exists for z c1 and z c2 at the third harmonic of the fundamental frequency for the crystal. in addition, care must be taken that the anegative resistanceo of the amplifier is not sufficient at the fundamental frequency to induce oscillation at the fundamental frequency. it may be necessary to add additional filtering to reduce the gain of the amplifier at the fundamental frequency. the key to achieving stable overtone oscillator operation is ensuring the existence of the above condition at the desired overtone while ensuring its failure at all other frequencies. l1 and c1 are chosen so that > f f 2 p l 1 c 1 1 where f f is the fundamental frequency of the crystal resonator. if l1 and c1 are chosen to be net capacitive at the desired overtone frequency and if the condition gm z c1 z c2 > r s is true only at the desired overtone frequency, the oscillator will oscillate at the frequency of the overtone. normally, l1 and c1 are not chosen to be resonant at the overtone frequency but at a lower frequency to ensure that the parallel combination of l1 and c1 is capacitive at the overtone frequency and inductive at the fundamental frequency. < f o 2 p l 1 c 1 1 f f < the net inductance of the rest of the resonant loop then balances this capacitance at the overtone frequency. 1 1 x ls x cs + x l2 + x l(stray) x c3 1 x c0 1 = 0 1 x c1 1 x l1 + l2 and c3 are chosen to provide the desired adjustment to the resonant overtone frequency. this is normally computed by calculating the expected ppm change at the resonant frequency and using this to define the value of the reactance necessary to produce this change. x (of l2 and c3) z (crystal at resonance) d f f (ppm) = d f f (ppm) = x(of l2 and c3)/z(crystal at resonance) the values needed for this calculation can be derived from the value of the fundamental frequency and c o . if c o is known or can be measured, c s is defined as 200 c o c s = for an at cut crystal. the fundamental frequency can be used to calculate the value for l s using either the series resonant or parallel resonant formulas given earlier. since the q of the crystal, r x q = is usually sufficiently large at the resonant frequency so that r s << z(crystal) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 33 motorola rf/if device data r s can be ignored. the value for c3 and l2 are chosen so that x c3 = x l2 when c3 is adjusted to approximately half its maximum capacitance. at this setting, the combination produces a zero change in the overtone frequency. if c3 is then chosen so that x c3 at minimum capacitance is [x c3 (max)] x l2 >= d f f (ppm) z(crystal) and l2 is approximately x c3 (max) 2 x i2 = then x c3 (max) >= 2[ d f f (ppm)] z(crystal) and x c (max) 4 x c (min)= this results in an adjustable change in the operating frequency of +[ d f f (ppm)] and [ d f f (ppm)] / 2. if ratios nearer to 1:1 are used for x c3 (max) and x l2 , the tuning range will be skewed with a wider [ d f f (ppm)] but at the expense of less adjustability over the +[ d f f (ppm)] range. figure 28. colpitts oscillator configured for overtone operation 0 0 c3 c2 c1 r1 r2 q1 m2 m1 +v osc b osc e frequency synthesizer i1 200/800 m a 0 x 1 0 c4 l1 l2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 34 motorola rf/if device data 7b. main loop filter design e conventional the current output of the charge pump allows the loop filter to be realized without the need of any active components. the preferred topology for the filter is illustrated in figure 29. the r o /c o components realize the primary loop filter. c a is added to the loop filter to provide for reference sideband suppression. if additional suppression is needed, the r x /c x realizes an additional filter. in most applications, this will not be necessary. if all components are used, this results in a fourth order pll, which makes analysis difficult. to simplify this, the loop design will be treated as a second order loop (r o /c o ), and additional guidelines are provided to minimize the influence of the other components. if more rigorous analysis is needed, mathematical/system simulation tools should be used. component guideline c a <0.1 x c o r x >10 x r o c x <0.1 x c o the focus of the design effort is to determine what the loop's natural frequency, w o , should be. this is determined by r o , c o , k p , k v , and n t . because k p , k v , and n t are given, it is only necessary to calculate values for r o and c o . there are three considerations in selecting the loop bandwidth: 1. maximum loop bandwidth for minimum tuning speed. 2. optimum loop bandwidth for best phase noise performance. 3. minimum loop bandwidth for greatest reference sideband suppression. usually a compromise is struck between these three cases, however, for a fixed frequency application, minimizing the tuning speed is not a critical parameter. to specify the loop bandwidth for optimal phase noise performance, an understanding of the sources of phase noise in the system and the effect of the loop filter on them is required. there are three major sources of phase noise in the phaselocked loop e the crystal reference, the vco, and the loop contribution. the loop filter acts as a lowpass filter to the crystal reference and the loop contribution. the loop filter acts as a highpass filter to the vco with an inband gain equal to unity. the loop contribution includes the pll ic, as well as noise in the system; supply noise, switching noise, etc. for this example, a loop contribution of 15 db has been selected. the crystal reference and the vco are characterized as highorder 1/f noise sources. graphical analysis is used to determine the optimum loop bandwidth. it is necessary to have noise plots from the manufacturers of both devices. this method provides a straightforward approximation suitable for quickly estimating the optimal bandwidth. the loop contribution is characterized as whitenoise or loworder 1/f noise, given in the form of a noise factor which combines all the noise effects into a single value. the phase noise of the crystal reference is increased by the noise factor of the pll ic and related circuitry. it is further increased by the total dividebyn ratio of the loop. this is illustrated in figure 30. the point at which the vco phase noise crosses the amplified phase noise of the crystal reference is the point of the optimum loop bandwidth. in the example of figure 30, the optimum bandwidth is approximately 15 khz. to simplify analysis further, a damping factor of 1 will be selected. the normalized closed loop response is illustrated in figure 31 where the loop bandwidth is 2.5 times the loop natural frequency (the loop natural frequency is the frequency at which the loop would oscillate if it were unstable). therefore, the optimum loop bandwidth is 15 khz/2.5 or 6.0 khz (37.7 krads) with a damping coefficient, z 1. t(s) is the transfer function of the loop filter. where n t = total pll divide ratio e 8 x n where (n = 25 ... 40), k v = vco gain 2 p hz/v, k p = phase detector/charge pump gain a =( |i oh | + |i ol | ) / 4 p . technically, k v and k p should be expressed in radian units [k v (rad/v), k p (a/rad)]. since the component design equation contains the k v x k p term, the 2 p cancels and the value can be expressed as ahz/v (amp hertz per volt). figure 29. loop filter charge pump ph/frq det n counter xtl osc pll vco c o c a r o c x r x r counter 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 35 motorola rf/if device data figure 30. graphical analysis of optimum bandwidth 60 70 80 90 100 110 120 130 140 150 db 10 100 1 k 10 k 100 k 1m hz vco optimum bandwidth closed loop response 20 x log (n t ) crystal reference 15 db nf of the noise contribution from loop natural frequency figure 31. closed loop frequency response for z = 1 1.0 k 10 0 10 20 30 40 50 60 0.1 hz 100 1.0 10 db 3 db bandwidth in summary, follow the steps given below: step 1: plot the phase noise of crystal reference and the vco on the same graph. step 2: increase the phase noise of the crystal reference by the noise contribution of the loop. step 3: convert the dividebyn to db (20log 8 x n) and increase the phase noise of the crystal reference by that amount. step 4: the point at which the vco phase noise crosses the amplified phase noise of the crystal reference is the point of the optimum loop bandwidth. this is approximately 15 khz in figure 30. step 5: correlate this loop bandwidth to the loop natural frequency per figure 31. in this case the 3.0 db bandwidth for a damping coefficient of 1 is 2.5 times the loop's natural frequency. the relationship between the 3.0 db loop bandwidth and the loop's anaturalo frequency will vary for different values of z . making use of the equations defined in figure 32, a math tool or spread sheet is useful to select the values for r o and c o . appendix: derivation of loop filter transfer function the purpose of the loop filter is to convert the current from the phase detector to a tuning voltage for the vco. the total transfer function is derived in two steps. step 1 is to find the voltage generated by the impedance of the loop filter. step 2 is to find the transfer function from the input of the loop filter to its output. the avoltageo times the atransfer functiono is the overall transfer function of the loop filter. to use these equations in determining the overall transfer function of a pll, multiply the filter's impedance by the gain constant of the phase detector, then multiply that by the filter's transfer function. figure 33 contains the transfer function equations for the second, third, and fourth order pll filters. pspice simulation the use of pspice or similar circuit simulation programs can significantly reduce laboratory time when refining a pll design. the following describes the use of behavioral modeling to develop useful models for studying loop filter performance. in many applications the levels of sideband spurs can also be studied. behavioral modeling is chosen, as opposed to discrete device modeling, to improve performance and reduce simulation time. pll devices can contain several thousand individual transistors. to simulate at this level can result in generation of an enormous amount of data when compared to a simpler behavioral model. for example, a logic nand gate can contain several transistors. each of these requires a data set for each of the transistor terminals. if a half dozen transistors are used in the gate design, both current and voltage measurements for each terminal of each device for every node in the circuit is calculated. the gate can be expressed as a behavioral model, which is treated and simulated as a single device. since pspice sees this as a single rather than multiple devices, the amount of accumulated data is much less, resulting in a faster simulation. for applications using integrated circuits such as plls, it is desirable to investigate the performance of the circuitry added externally to the integrated circuit. by using behavioral modeling rather than discrete device modeling to represent the integrated circuit, the engineer is able to study the performance of the design without the overhead contributed by simulating the integrated circuit. phase frequency detector model the model for the phase frequency detector is derived using the waveforms shown in figure 20. two signals are present at the input of the phase frequency detector. these are the reference input and the feedback from the vco and/or prescaler. the two signals are compared to determine the lag/lead relationship between the two signals and pulses generated to represent the leading edge of each signal. a pulse whose width equals the lead of one input signal over the other is generated by an rs flipflop (rsff). one rsff generates a pulse whose width equals the lead of the reference signal over the feedback signal, and a second rsff generates a signal whose width is the lead of the feedback signal over the reference signal. the logical model for the phase frequency detector is shown in figure 34. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 36 motorola rf/if device data figure 32. design equations for the second order system r o c o s + 1 t(s) = s 2 + r o c o s + 1 nc o k p k v = s 2 + 1 w o 2 s + 1 2 z w o s + 1 2 z w o nc o k p k v = 1 w o 2 w o = nc o k p k v r o c o = 2 z w o z = w o r o c o 2 c o = n w o 2 k p k v r o = w o c o 2 z figure 33. overall transfer function of the pll z lf (s) = c o s r o c o s + 1 v t c o v p r o for the second order pll: for the third order pll: for the fourth order pll: v t c o v p r o c a v t c o v p r o c a c x t lf (s) = v p (s) v t (s) = 1 , v p (s) = k p (s)z lf (s) z lf (s) = c o r o c a s 2 + (c o + c a )s r o c o s + 1 t lf (s) = v p (s) v t (s) = 1 , v p (s) = k p (s)z lf (s) z lf (s) = c o r o c a r x c x s 3 + [(c o + c a )r x c x + c o r o (c x + c a )] s 2 + (c o + c a + c x )s (r o c o s + 1) (r x c x s + 1) t lf (s) = v p (s) v t (s) ,v p (s) = k p (s)z lf (s) = (r x c x s + 1) 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 37 motorola rf/if device data figure 34. phase frequency detector logic diagram pg1 pulse generator pg2 rsff2 rsff1 ref in r s p1 out in r f v f pulse generator s r p1 out in the behavioral model of the phase frequency detector shown in figure 35 is derived using the phase frequency detector logic diagram. behavioral models for the pulse generator, and gate (figure 36), and rs flipflops (figure 37) are created using analog behavioral blocks. the pulse generator is created using a delay block and a agateo defined by the behavioral expression: if [v(v1) 1 & v(v2) , 1, 5, 0] v1 and v2 represent the two inputs to the block. this is the behavioral expression for an and gate with one input inverted. the addition of the delay element produces a pulse whose width equals the delay element. the pulses appearing at the output of hb1 and hb2 (figure 35) are used to set the flipflops, rsff1, and rsff2. the leading pulse will set the appropriate flipflop resulting in a high at the output of that flipflop. the output of this flipflop will remain high until the arrival of the second (or lagging) pulse sets the second rs flipflop. the presence of a high on both rs flipflop outputs results in the generation of the reset pulse. the reset pulse is generated by the analog behavioral block (configured as an and gate) and the delay element. the delay element is necessary to eliminate the zero delay paradox of input to output to input. the output of the phase frequency detector is two pulse trains appearing at r f and v f . when the pll is locked, the pulses in both pulse trains will be of minimum width. when the phase frequency detector is out of lock, one pulse train will consist of pulses of minimum width while the width of the pulses in the second train will be equal to the lead/lag relationship of the input signals. if the ref input leads `in', the pulse train at r f will consist of pulses whose width equals the lead of ref. if ref lags `in', the width of the pulses appearing at v f will equal this lag. the terms lead and lag used in this explanation represent an occurrence in time rather than a phase relationship. at any condition other than locked, one input (either in or ref), will be of a higher frequency. this results in the arrival of the pulse at that input ahead of the pulse at the other input, or leading. the second then is lagging. to simulate the operation of the phase frequency detector in an actual circuit, a charge pump needs to be added. the behavioral model for this is shown in figure 38. two voltagetocurrent behavioral models are used to produce the charge pump output. two voltagecontrolled switches with additional behavioral models, monitor the voltage of the output of the charge pump and clamp to 0 or v cc to simulate a real circuit. to ensure the model conforms to the pll, the delay blocks in the phase frequency detector should be set to the expected value as specified by the MC145181 data sheet. in addition, the charge pump sink and source current behavioral model should also be set to deliver the desired current and v cc specified to ensure correct clamping. modeling the vco the vco (figure 39) is also modeled using analog behavioral modeling (abm). the model used in the following examples assumes a linear response; however, the control voltage equation can be modified as desired. the circuit is modeled as a sine generator controlled by the control voltage. the sine generator can be modeled using the evalue function or the abm function. in figure 39, the evalue function is used to generate the divided output and the abm function is used for the undivided output. either the gvalue or the abm/i function can be used for the control voltage. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 38 motorola rf/if device data figure 35. behavioral model of the phase frequency detector ref in r f v f v1 v2 out hb2 if [v(q1)>=1 & v(q2)>=1, 5, 0] rsff1 r s p1 delay s r p1 rsff2 out in delay in out pulse generator v2 v1 out hb1 delay in out pulse generator figure 36. behavioral block used for the pulse generator v1 v2 v2 out if (v(v1) 1 | v(v2) < 1, 5, 0) v1 figure 37. behavioral block used as an rs flipflop if [v(in1)>=1 & v(in2)<1 | v(in2)<1, 5] q out s r in3 in2 in1 if [v(in2)>=1, 0] if [v(in3)>=1 & v(in2)<1, 5, 0] if [v(q)>=1, 5, 0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 39 motorola rf/if device data figure 38. charge pump model if [v(in1)>=1 v(in2)<1, 1 x 10 3 , 0] + 0 pd out in1 in2 0 0 if [v(in2)>=1 v(in1)<1, 1 x 10 3 , 0] s1 sbreak + 0 if [v(idrive) > 0, 0, 1] if [v(idrive) < 5, 0, 1] s2 + 0 + 0 + sbreak 5 v1 idrive r f v f figure 39. vco behavioral model 5 v 0 v 1 x 10 99 r1 sin {t w [f c time + n v(int)]} 1 1 x 10 3 1 x 10 6 + parameters: t w f c k1 6.283 250 x 10 6 525 x 10 6 parameters: n q c 5000 1 x 10 6 in+ in out+ out evalue 0 ctrl in+ in gvalue g1 e1 c1 int ctrl out vco out ic = 0 n time + v(int) f c t w n v(ctrl) q c k1 sin t w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 40 motorola rf/if device data the equation for the sine generator is: n f c time + v(int) . e = sin t w f c is defined as the output frequency when the control voltage is 0. this is the expected vco frequency before frequency division. for the purpose of simulation, the counter value, n, has been written into the equation to ensure the correlation between the modeled circuit and the mathematical loop filter calculations. t w is 2 p ; additional decimal places can be added as needed. v(int) is the control voltage effect and is defined in these examples as: t w n k1 v(cntl) 1 x 10 6 . v(int) = where k1 is the vco gain in rad/v. the value c1 in the schematic of the vco can be arbitrarily changed; however, the value must match that of q c . q c determines the value of the current to be integrated by the capacitor c1. r1 is arbitrarily set to 1 x 10 99 and is not an active part of the circuit; however, it must be included to prevent open pin errors from the pspice software. the gvalue function is used to perform the generation of v(int). there is some interaction between the integrator, (gvalue output and c1) and r1. v(int) is a continuous ramp that is loaded by the resistance of r1. unless the gvalue output current is sufficiently large for the value chosen for r1, the vco control voltage required to maintain lock will increase throughout the simulation producing nonlinear operation. modifications to the circuit can be performed either by changing the values in the parameter list or for major changes to the vco characteristics, the equations for the sine generator, or control voltage can be altered. the output of the sine generator is amplified by 1000 to produce a sharp rise/fall time and the output limited to swing between the values of 0 v and 5 v to convert it to a digital output. the resultant circuit/symbol accepts a voltage input from the loop filter and produces a square wave output at the desired frequency. this frequency should be chosen to represent the frequency present at the output of the n counter of the pll frequency synthesizer. the second output represented by the abm function is a sine wave output of the frequency expected from the actual vco. the primary purpose of this output is to allow full frequency simulation for spectrum analysis. by running a transient analysis of sufficient time, it is possible to determine spur content and level. if sufficient resolution is used in the simulation, the pspice probe fft transform can be used to provide the typical spectrum analyzer display. loop filter simulation the circuit shown in figure 40 is used to simulate the closed loop operation for a single charge pump output. component values for the loop filter should be computed using information from the previous section. initial conditions can be set using the aic1o symbol with starting values specifying the initial condition. by adjusting component values for the loop filter, performance of the closed loop operation can be monitored. the control voltage to the input of the vco can be monitored for a variety of conditions including settling time, lock time, and ripple present at the vco input. in addition, the output of the vco can be monitored for spur sidebands caused by ripple on the loop filter output; however, expected operation at high frequencies may be difficult due to the excessive data that can be generated. as the divider ratio, n, increases for a fixed step frequency, the number of data points required to obtain sufficient information to overcome aliasing problems may become excessively large. in addition, the number of samples required should be three or more per cycle. for vco frequencies in the range of 500 mhz, this means the step ceiling needs to be in the range of 100 to 500 ps. if a simulation time of 1 ms is needed, the actual computer time can be several hours with data accumulation in the 1 to 2gbyte range. figure 40. pll closed loop model u3 ref in hb2 r3 75 k 0 0 c2 c3 00 1 k r4 ctrl + + + ic = 3.5 0.1 n 0 c1 v1 out vco out 7.5 k ic = 3.5 pd out r f hb1 v f r f v f 0.2 n 2 n r1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 41 motorola rf/if device data 7c. main loop filter design e adapt introduction for pspice simulation, the schematic model shown in figure 41 was chosen. the classical pll model employing a phasefrequency detector, a vco, and an adaptive loop filter is used to simplify visualization of circuit operation. the parameter tables allow for modification of circuit performance by providing an easy method for altering critical values without necessitating changes to sublevel schematics. the definition for the terms are: t w =2 p , f r = reference frequency, t d = time delay; allows delay of the start of the high current mode (used to perform reference spur measurements), cpl = charge pump low current, cph = charge pump high current, n = n counter value, s z = amount the n counter is being increased (or decreased) by, s t = number of f r cycles that cph is active; this value is either 16, 32, 64, or 128, vcphh = charge pump voltage high, vcphl = charge pump voltage low, k1 = vco gain (hz/volt), f c = vco frequency at 0 v control voltage, h = reference spur scaling factor. modeling the phasefrequency detector figure 42 is a schematic of the phasefrequency detector. it includes the reference oscillator model, phasefrequency detector model, and charge pump models. v1 is the control element used to generate the step time for switching between cpl and cph. the signal source vpulse, is used to simulate the timer that controls when cpl and cph are turned on. pw calculates the pulse width that simulates the counter from the values for s t and f r that are entered in the parameter tables on the top level schematic. figure 41. top level pll model 50 p pd out lo in hb2 c2 20 k 0 0 c5 c6 0 0 1 k r10 ctrl 330 p c4 out vco hb1 33 p r3 parameters: t w f r h 6.283185308 25 k 1 parameters: cpl cph k1 1 x 10 3 4 x 10 3 4 x 10 6 parameters: n s z s t 29320 400 32 pd out hi + + 60.4 k r1 c1 40.2 k + + 3300 p 10% 330 p c3 330 p r2 parameters: vcphh vcphl f c 5 0 727.6 x 10 6 parameters: t d 0 k1 ic = f r n f c k1 ic = f r n f c k1 ic = f r n f c k1 ic = f r n f c figure 42. phasefrequency detector with dual charge pumps hb1 shift + hb3 hb2 pd out lo pd out hi pd out hi pd out lo r f v f r f v f f in ref ref shift v1 0 in shift pw = 4 f r s t t d = f r 4 t d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 42 motorola rf/if device data reference oscillator the reference oscillator is shown in figure 43. the oscillator is modeled using an analog behavioral block. the function for the block is written as an aifo condition. if the signal shift is low, the reference frequency f r will be generated if shift is high, a signal of four times f r will be generated. the limiter/gain block converts the low level sine wave output of the analog behavioral block into a square wave. the values of 0 for the low value and 5 for the high value are used throughout. these values are chosen out of habit and are not critical in an analog behavioral environment, providing the conformity is universal throughout the design. figure 43. reference oscillator if [v(shift) < 1, sin (t w f r time), sin (t w f r time) 4] shift 5 v 0 v 1 k ref shift phasefrequency detector the actual phasefrequency detector model minus reference oscillator and charge pumps is shown in figure 44. the detector is composed of three delay modules: a behavioral and gate, and two rs flipflops. the stp function resets the phase/frequency detector logic on initiation of the simulator. the circuit for the behavioral rs flipflop is shown in figure 45. the rs flipflop equation illustrates the benefit of using the behavioral block instead of using a primitive logic element. a delay block and the behavioral gate equation generate a pulse whose width is equal to the value of the delay block. to generate the output using a primitive logic element such as a nand gate, an inverter would be necessary to invert one of the nand inputs. this approach requires three elements to be used instead of the two of the behavioral approach just for the pulse generator. in the behavioral approach, the equation for the behavioral and gate is folded into the rs flipflop, eliminating a separate gate altogether. constructing the model with classic logic elements would require two nor gates for the flipflop, a delay element, an inverter, and an and gate; five elements as compared with three for the behavioral approach. since the rs flipflop is used in two places in the model, four less components are needed for simulation. since the speed of the simulation is directly impacted by the number of components being simulated, any reduction in the total number of components is a savings in simulation time and computer memory. the rs flipflops generate the lead or lag outputs that are used to asteero the vco. the pulse generator equation produces narrow pulses coincident with the leading edge of each of the input signals. these pulses set the appropriate rs flipflop. once set, the leading flipflop must wait until the lagging flipflop is also set. the behavioral and gate provides the necessary output pulse to reset the flipflops. the delay element placed at the output of the behavioral and gate prevents an undefined state for the detector. the value 5 ns is chosen to correspond with the data sheet. the logic functions as a three state phase/frequency detector with an operating range of 2 p . r f and v f deliver positive pulses, whose width represents the amount of the lead of each input over the other input. figure 44. phasefrequency detector logic q1 hb1 ref in in2 in1 q out r f v f delay 5 ns q2 in2 in1 q out hb2 if [v(q1)>=1 & v(q2)>=1 | v(delay)>=1, 5, 0] 5 stp (5 ns time) delay f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 43 motorola rf/if device data figure 45. behavioral rs flipflop if [v(v1)>=1 & v(v2)<1 & v(in2)<1, 5] q out q in1 in2 delay 1 ns in3 u1 in2 v1 v2 if [v(in2)>=1, 0] if [v(in3)>=1 & v(in2)<1, 5, 0] if [v(q)>=1, 5, 0] charge pump model the schematic used for the charge pump in the phasefrequency detector model is shown in figure 46. each charge pump is made from two analog behavioral blocks. the blocks chosen are three input behavioral blocks with current outputs. the two blocks are connected in pushpull to generate the appropriate source and sink output. the output of each block is defined using an aifo statement to monitor the input signals and generate the correct output at the appropriate time. one note about this type of design. spice does not limit the output voltage swing necessary to generate the programmed current. it is possible to implement values for the loop filter, which will cause the charge pump to exceed the rail voltage. to limit the output voltage to prevent exceeding the value of the rails, the two behavioral blocks, voltagecontrolled switches s1 and s2, and constants vcphh and vcphl are added. s1 and s2 on/off resistance is set to 1 w and 1 x 10 12 w , and the off/on voltage is set to 0 v and 1 v to correspond to the behavioral blocks. the values defined by the constants are accessible from the parameter tables on the top level schematic. vco model the model used for simulating the vco is shown in figure 47. the vco is composed of a sine wave generator and a control element. an analog behavioral block is used as a sine wave generator and a gvalue element is used as a control element. the gvalue is operated as an integrator. the output of the integrator is defined as v(int) = k1 v(ctrl) q c . the block designated to provide the feedback to the phasefrequency detector uses a single input analog behavioral block. the signal shift generated by v1 in the phasefrequency detector block is used to define the output frequency of the behavioral block. in this manner, the switching of the n and r values for the programmable counters can be simulated. in the implementation shown, the two frequencies will be either 25 khz or 100 khz when locked to the reference oscillator. the other behavioral block is used to generate a vco output dependent on the loop, but not contributing to the operation of the loop. this is used to emulate the actual vco output with one modification. aho has been added to the equation generating the sine wave. if h is defined as 1, the sine wave generated will be the same as the expected vco output. if h is chosen as some value greater than 1, the frequency of the output will be reduced accordingly. this is useful when running simulations designed to show reference spur levels. in cases where it is desirable to view reference spur levels, simulation can become difficult or impossible. for example, consider the circuit that is being discussed. this circuit represents the evaluation kit (mc145230evk) using a vco tunable between 733 mhz to 742 mhz, with a step frequency of 25 khz. note this example is for reference only. the maximum operating frequency of the MC145181 is 550 mhz. operation of the vco at frequencies greater than 550 mhz requires the inclusion of additional external division such as a prescaler. to obtain useful information from the simulation, a sampling rate greater than the nyquist limit must be used (three to five samples per cycle). this dictates a step size less than 1/2 nanosecond. additionally, the reference frequency is only 25 khz. to accurately represent the conditions for spur generation, the simulation time must be long enough to include a sufficient number of f r periods. otherwise, no spurs are generated. in addition, the data file system is limited to 2 gbyte, either in the nt 4.0 operating system or in pspice itself. if the file exceeds 2 gbyte, the data is discarded. to simulate reference spur generation at 730 mhz, a 1 ms simulation time was chosen. the simulation ran for several hours and generated a data file just under 2 gbyte. the result is shown in figure 48. the plot obtained from the evk is shown in figure 49 for comparison. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 44 motorola rf/if device data figure 46. cpl and cph charge pumps if [v(in1)>=1 & v(in2) <1 & v(shift) <1, cpl, 0] in1 in2 0 0 if [v(in2)>=1 & v(in1) <1 & v(shift) <1, cpl, 0] shift if [v(in1)>=1 & v(in2) <1 & v(shift) >= 1, cph, 0] if (v(in2)>=1 & v(in1)<1 & v(shift) >= 1, cph, 0) pd out lo pd out hi r f v f shift 0 0 + 0 s4 + if [v(idrv) > vcphh, 1, 0] if [v(drv) < vcjphl, 1, 0] s5 + 0 + sbreak drv vcphh vcphl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 45 motorola rf/if device data figure 47. vco model parameters: q c 1 x 10 6 5 v 0 v out vco 1 x 10 6 turbo shift 1 x 10 99 r1 1 x 10 6 + 0 ctrl in+ in gvalue g1 c1 int ctrl ic = 0 k1 v(ctrl) q c f c time + v(int) h sin t w if (v(turbo) <1, sin f c time + v(int) n + s z t w , sin f c time + v(int) n + s z 4 t w figure 48. reference spur simulation at 730 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 46 motorola rf/if device data figure 49. sybil evk reference spur measurements 10 20 30 40 110 50 60 70 80 90 100 center 737.5000009 mhz span 64 khz 1avg 1sa 10 0 6.4 khz 25.00000000 mhz 10 dbm ref lvl 73.32 db swt 130 ms unit dbm 1 1 it should be noted that the reference spur values obtained from the simulation are lower than the values obtained from the actual evk. this is because the simulation model is an aidealo modeling of the pll. to obtain results closer to the actual implementation, the models should be amassagedo to be more representative of the actual circuit. for example, spur levels more consistent with actual circuitry can be obtained by adding a resistance to ground at the input of the vco to represent leakage. the value chosen should be consistent with vco and circuit component performance. to reduce simulation time, the h value may be used. by reducing the frequency of the vco output, the number of samples required for simulation can also be reduced. the output shown in figure 50 shows the result of dividing the vco output of 730 mhz by 7.3 to produce a 100 mhz output. the reference spurs are better represented since adequate simulation time is possible. to generate these outputs, the parameter values used were those shown on the top level schematic. the simulator was set to run a transient sweep, with t d set for a delay that would prevent the 4x frequency from being started. the initial conditions were set to 1 v and the simulation run for 1 ms. vco was monitored and the probe display button fft was initiated. the x and y axis were adjusted to those shown. note: these simulations are presented as the result of aidealo models and may not accurately display real hardware. it would be best to load the vco input with additional leakage devices such as a large resistance, to accurately display real conditions. these models are starting points for more accurate implementations. loop filter analysis is more accurate, since the predominate factors are in the loop filter itself. to simulate the performance of the loop filter, t d is set for 0, n is set to the desired divider value, and s z is set to the desired step. for this example, 733 mhz was chosen. note these values are for reference only. the maximum operating frequency of the MC145181 is 550 mhz. for vco frequencies greater than 550 mhz, an added external divider such as a prescaler is necessary. with the vco model shown, v(ctrl) = 0 produces an output of 727.6 mhz and at v(ctrl) = 1.35 v, the vco frequency would be 733 mhz; the minimum mc145230evk default operating frequency. to show the response of the loop filter to a 10 mhz step at this operating frequency, s z = 10 mhz / 25 khz = 400. the simulation is run for 1 ms with a step ceiling of 100 ns. the result is shown in figure 51. if the simulation is examined over a longer period of time, the long term settling can be compared to the performance of the actual circuitry. the plot shown in figure 52 shows the vco control voltage with the display resolution set to 1 mv. this compares to the plot of frequency variation measurements made on the actual evk. this plot is shown in figure 53. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 47 motorola rf/if device data figure 50. h set to generate a 100 mhz output figure 51. 10 mhz step for an operating frequency of 729 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 48 motorola rf/if device data figure 52. vco settling figure 53. frequency settling of the evk freq c tlk only waiting for trigger vertical top/ bottom ref int 200.0 m s/div t 0.00s 0.00 s 2 center/ span 741.999715m z h center span find center find center 8.000k z h z h 1.000k /div 2.0000 ms and span 1.000 ms t 742.2 m s 1 d 742.2 m s 742.003715mhz 741.999715mhz 741.995715mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 49 motorola rf/if device data it is noted that the results obtained from the simulation compare favorably to those obtained from the measurements of the evk. the simulation display resolution is adjusted to represent the same 4 khz deviation as shown in figure 53. since variation in vco control voltage is equal to the vco frequency divided by the vco gain, this axis may be redefined to show change in frequency rather than change in control voltage. the models shown represent a askeletono that may be used to develop extensive and reliable simulations that can greatly reduce actual breadboarding and testing. in addition to the basic simulations shown, pspice provides a method by which worst case and monte carlo evaluation can be performed on all, or selected components. by limiting the circuit to minimum necessary components, simulation can be performed using only the pspice evaluation copy. in addition, the optional pspice program optimizer should allow refining the loop filter more easily. while pspice is a powerful tool, it is not without limits. since it was designed to run on large mainframe computers, the pc is just now becoming powerful enough to make use of the capability of the simulator. a fast pentium class processor with a large ram and a hard drive of the gbyte size is a necessity. even with the most judicious planning, some simulations will abumpo the limits of the system. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 50 motorola rf/if device data 7d. secondary loop filter design low pass filter design for pd out the design of low pass filtering for pd out for the device can be accomplished using the following design information. in addition to the example included here, motorola application note an1207, also includes examples of active filtering which may be used to supplement this information. f(s) = w n = (r 1 + r 2 )sc + 1 r 2 sc + 1 c vco r 2 pd out r 1 nc(r 1 + r 2 ) r 2 c + n k f k vco z = 0.5 w n k f k vco definitions: n = total division ratio in feedback loop k f (phase detector gain) = v dd /4 p v/radian for pd out k f (phase detector gain) = v dd /2 p v/radian for f v and f r k vco (vco gain) = 2 pd f vco d v vco for a nominal design starting point, the user might consider a damping factor z 0.7 and a natural loop frequency w n (2 p f r / 50), where f r is the frequency at the phase detector input. larger w n values result in faster loop lock times and, for similar sideband filtering, higher f r related vco sidebands. recommended reading: gardner, floyd m., phaselock techniques (second edition). new york, wileyinterscience, 1979. manassewitsch, vadim, frequency synthesizers: theory and design (second edition). new york, wileyinterscience, 1980. blanchard, alain, phaselocked loops: application to coherent receiver design. new york, wileyinterscience, 1976. egan, william f., frequency synthesis by phase lock. new york, wileyinterscience, 1981. rohde, ulrich l., digital pll frequency synthesizers theory and design. englewood cliffs, nj, prenticehall, 1983. berlin, howard m., design of phaselocked loop circuits, with experiments. indianapolis, howard w. sams and co., 1978. kinley, harold, the pll synthesizer cookbook. blue ridge summit, pa, tab books, 1980. seidman, arthur h., integrated circuits applications handbook , chapter 17, pp. 538586. new york, john wiley & sons. fadrhons, jan, adesign and analyze plls on a programmable calculator,o edn . march 5, 1980. an535, phaselocked loop design fundamentals, motorola semiconductor products, inc., 1970. ar254, phaselocked loop design articles, motorola semiconductor products, inc., reprinted with permission from electronic design, 1987. an1207, the mc145170 in basic hf and vhf oscillators, motorola semiconductor products, inc., 1992. an1671, mc145170 pspice modeling kit, motorola semiconductor products, inc., 1998. example: given the following information: vco frequency = 45.555 mhz, frequency step size = 5 khz, vco gain = 3.4 mhz/v. design a loop filter with a damping factor of 0.707. the vco is assumed to have a linear response throughout the range used in this example. the gain for the vco has been given as 3.4 mhz/v and is multiplied by 2 p rad/s/hz for calculating loop filter values. k vco = 2 p rad/s/hz x 3.4 mhz/v = 2.136 x 10 7 rad/s/v . the gain for the phase detector is defined as 4 p v dd k f = v/rad for pd out . using a value for v dd (phase detector supply voltage) of 3.6 v with the output voltage multiplier turned off, the value is 4 p 3.6 k f = = 0.2865 v/rad . let 50 2 p f r w n = = 628.3 rad/s and 45.555 mhz = f vco f step size 5 khz n = = 9111 . choosing c = 0.05 m f and calculating r1 + r2, n c w n 2 k f k vco r1 + r2 = = 34 k w . with a damping factor of 0.707, c = 15 k w , n k f k vco 0.707 0.5 w n r2 = r1 = (r2 + r1) r2 = 34 k 15 k = 19 k w 20 k w . the choice for c is somewhat arbitrary, however, its value does impact the performance of the loop filter. if possible, a range of choices for c should be used to calculate potential loop filters and the resultant filters simulated, as will be shown below, to determine the best balance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 51 motorola rf/if device data if additional filtering is desired, r1 may be split into two equal resistors and a capacitor to ground inserted. since the closest resistance to onehalf of 9 k is 4.7 k w , this value is chosen for r1 a and r1 b . the maximum value for the added capacitance is based on the bandwidth of the original loop filter. the general form for the transfer function for the passive filter shown in figure 54, can be shown to have the form: s + w 2 (s + w 1 ) (s + w 3 ) f(s) = k h where (r1 a + r1 b + r2) c 1 w 1 = , r2c 1 w 2 = , (r1 + r2) 1 r1 a r1 b + r1 a r2 w 3 = , c c where r1 = r1 a + r1 b and w 3 > w 2 . since splitting r1 into two equal values, r1 a and r1 b, and inserting the capacitance between the junction of r1 a and r1 b does not change the position of the pole located at w 1 , the value of w 1 remains (r1 a + r1 b + r2) c 1 w 1 = . = (r1 + r2) c 1 the 0 identified at w 2 = 1/r2 c is also unaffected by the addition of c c if w 3 > w 2 . since 2 r1 r1 a = r1 b = . the value of c c can be determined by specifying the value for w 3 and using the values already determined for r1 and r2. the rule of thumb is to choose w 3 to be 10 x w b so as not to impact the original filter. w b can be found as (2 + 4 z 2 + 4 z 4 )] w b = w n [1 + 2 z 2 + w b = 628.3 rad/s (2+ 4 (0.707) 2 + 4 (0.707) 4 )] [1 + 2 (0.707) 2 + = 1.293 x 10 3 rad/s . 10 w b = 12.93 x 10 3 rad/s . the circuit for the passive loop filter is shown in figure 54. r1 is split into two equal values and c c inserted at the junction of r1 a and r1 b . using the values defined above, c c is determined to be (r1 + r2) w 3 1 r1 a r1 b + r1 a r2 c c = (r1 + r2) 10 1 r1 a r1 b + r1 a r2 = = 10.83 nfd 10 nfd . w b w 3 figure 54. passive loop filter for pd out r1 a 10 k 0 0 c 15 k 10 k r1 b + 10 n 0 c c v1 ic = 0 50 n r2 v open loop ac analysis of the loop filter ac analysis is chosen for the mode of simulation for pspice and vsin is chosen for v1 and is set to produce a 1 v peak output signal. the simulation is then run and the result shown in figure 55. a bode plot of the loop filter is obtained which describes the open loop characteristics of the loop filter. the corner frequencies of the filter can be modified and the simulation rerun until the desired wave shape is obtained. since ac analysis runs much faster than transient analysis, the ac open loop analysis of the loop filter is much quicker and requires less resources than the closed loop transient analysis. closed loop filter simulations using pspice the top level schematic for simulating a simple loop filter for pd out operating closed loop, is shown in figure 56. this filter uses the values calculated above. the schematic represents the pll function using the internal phase detector, pd out , the loop filter calculated above, and a vco. the parameter table allows altering the divider value of n, the maximum current obtained from pd out , and pd out charge pump voltage from the top level schematic. the schematic for the vco is shown in figure 57. analog behavioral modeling is used rather than discrete transistor modeling to reduce component count and improve simulation efficiency. the behavioral vco is composed of an integrator that transforms the input ctrl into the voltage control v(int) and a sine wave generator function whose frequency is controlled by v(int). evalue and gvalue functions are used to perform the transforms. the analog behavioral models, abm and abmi, can also be used. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 52 motorola rf/if device data figure 55. bode plot of the passive loop filter figure 56. passive loop filter hb1 ref in hb2 r1 10 k 0 0 c2 15 k 10 k r6 ctrl + + + ic = 0 10 nf 0 c4 v2 out ic = 0 pd out 50 nf r2 parameters: cp n 0.3 ma 9111 parameters: vcph vcpl 3.6 0 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 53 motorola rf/if device data figure 57. vco behavioral model 1 x 10 99 r1 1 x 10 6 1 x 10 6 + parameters: t w f c k1 6.283 38.756 x 10 6 21.36283005 x 10 6 parameters: q c 1 x 10 6 in+ in out+ out evalue 0 ctrl in+ in gvalue g1 e1 c1 int ctrl out ic = 0 time + v(int) n f c sin t w v(ctrl) q c t w n k1 5 v 0 v g1 performs the operation [k1/(t w n)] v(ctrl) q c . this integrates the input ctrl to produce a voltage ramp used by e1 to produce the desired output. this input is integrated by c1 whose value should equal q c for most applications. r1 is required by spice to prevent a floating node error. e1 performs the calculations necessary to generate a sine wave of the desired frequency based on the values listed in the parameter tables and the value of ctrl. the output of e1 is multiplied by 1 x 10 6 and limited to 0 and 5 to obtain a square wave with a fast rise/fall time. since i/o_stm is a standard model whose values are 0 and 5, these are used here and in the phase detector rather than modifying the component libraries. the parameter tables provide a convenient method for setting vco parameters. t w is 2 p , f c is the zero control voltage vco frequency, and k1 is the vco gain in rad/s/v. the subschematic for the phase/frequency detector section of the drawing is shown in figure 58. this is composed of two blocks, hb3 and hb4. hb3 performs the pd out function with hb4 performing the actual phase detector operation. the circuit for the phase/frequency detector is shown in figure 59. the model is made up of two pulse generators, two rs flipflops, and appropriate behavioral gates. hb1 and hb2 are rs flipflops. these are constructed from behavioral blocks as shown in figure 60. a behavioral and gate with a 5 ns delay completes the three state ( 2 p ) phase/frequency detector. the stp function ensures the rs flipflops are reset at initiation. to perform the phase detector function, the ref and f in inputs of the behavioral rs flipflops are configured to simulate edge triggered operation. this is achieved by placing a 1 ns delay in the ref and f in signal paths. the input and output of the delay are compared by the input behavioral block and interpreted as a 1 ns pulse. these pulses are used to set hb1 and hb2. if f in leads ref, the in flipflop, hb2, will be set first. when ref leads f in , the ref flipflop, hb1, will be set first. the lagging edge drives the second flipflop output high and the behavioral and gate then resets both flipflops. the delay line at the output of the behavioral and gate prevents pspice from being confused and also completes the simulation of the phase detector. the outputs of the two rs flip=flops are labeled r f and v f . the time between the leading and lagging edges is reflected in the pulse width of the leading edge flipflop. the lagging edge flipflop will display a narrow pulse equal in width to the value chosen for the delay at the output of the behavioral and gate. this should be programmed to the minimum value as specified by the data sheet and is usually 5 ns or less. since the outputs r f and v f are pure logic signals, additional circuitry is necessary to produce the output pd out . this output should be high impedance when not driving, and pull either high or low depending on which function (r f or v f ) is active. the circuitry shown in figure 61 performs this function. to eliminate the need for discrete modeling of pd out , analog behavioral modeling is used. analog behavioral blocks abmi/2, generate a current source/sink output whenever the appropriate input is high. a second set of behavioral blocks monitor the output idrive, and switch on the appropriate voltage controlled switch whenever the output rises to the value of v dd (phase detector supply voltage) or drops to 0. to model pd out , either a model of the transistors used for pd out must be used or this behavioral arrangement can be used. since the output is specified by a specific output level and current capability, this arrangement suffices. the output swing becomes vcph in the schematic and the current capability is cp. if a nonzero value is desired for v lo , the value vcpl is adjusted from the parameter table on the top level schematic. this arrangement allows setting the output voltage swing of pd out by specifying vcph, the current drive of pd out by specifying the desired value for cp, and leakage values can be simulated by setting the appropriate attributes for s1 and s4 or by adding additional resistance. simulation figures 62 and 63 are the simulation results of running a transient analysis on the example shown above. the time to lock from power on is simulated by setting the initial condition (ic1) to 0 and running the simulation. figure 62 is the time versus value of the vco control voltage. figure 63 shows the output at the input of the loop filter and can be used to determine lock time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 54 motorola rf/if device data figure 58. phase/frequency detector hb4 f in ref r f v f r f v f pd out hb3 ref in pd out figure 59. phase detector logic q1 hb1 ref in in2 in1 q out r f v f delay 5 ns q2 u10 in2 in1 q out hb2 if [v(q1)>=1 & v(q2)>=1 | v(delay)>=1, 5, 0] 5 stp (5 ns time) figure 60. behavioral rs flipflop if [v(v1)>=1 & v(v2)<1 & v(in2)<1, 5] q out q in1 in2 delay 1 ns in3 u5 in2 v1 v2 if [v(in2)>=1, 0] if [v(in3)>=1 & v(in2)<1, 5, 0] if [v(q)>=1, 5, 0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 55 motorola rf/if device data figure 61. r f /v f to pd out conversion if (v(in1)>=1 & v(in2)<1, cp, 0) + 0 pd out in1 in2 0 0 if (v(in2)>=1 & v(in1)<1, cp, 0) s1 sbreak + if (v(idrive)> 0, 0, 1) if (v(idrive)< 5, 0, 1) s4 + 0 + sbreak r f v f idrive vcpl vcph figure 62. vco control voltage versus time f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 56 motorola rf/if device data figure 63. pd out at input to loop filter summary pspice provides a method by which the performance of pll circuitry can be simulated prior to, or in addition to, laboratory testing. the use of behavioral modeling allows the creation of simulation circuits that can provide valuable information for loop filter design and adjustment. by judicious attention to vco modeling, expected output characteristics can be verified prior to laboratory testing. while simulation does not replace laboratory testing, it can be used to find solutions to awhat ifo questions without the need for extensive empirical data gathering. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 57 motorola rf/if device data 7e. voltage multiplier stall avoidance there are three important criteria to note, highlighted in the following sections: allowing for voltage build, ensuring valid counter programming, and allowing for overshoot. violation of any of these may cause the voltage multiplier to collapse. once the voltage collapses, the loop goes out of lock and can not recover until the voltage is allowed to build up again. for an active loop, the voltage multiplier is designed to maintain the multiplied voltage on the phase/frequency detector supply pin (c mult ). if the main loop is active, the multiplier cannot build the voltage. allowing for voltage build after power up, a sufficient time interval must be provided for the onchip voltage multiplier to build up the voltage on the c mult pin. during this interval, the phase/frequency detector outputs for the main loop (pd out hi and pd out lo) must be inactive (floating outputs). the por (poweron reset) circuit forces this afloato condition, thus allowing the voltage to build on the c mult pin. the duration of the interval to build the voltage is determined by the external capacitor size tied to the c mult pin and the charging current which is 100 m a minimum. the following formula may be used: t = cv / i where t is the interval in seconds, c is the c mult capacitor size in farads, v is the desired voltage on c mult in volts, and i is the charging current, 1 x 10 4 amps. the desired voltage on c mult is 4 v for a nominal 2 v supply and 5 v for any supply above 2.6 v. after this interval, the chip can maintain the voltage on the c mult pin and the phase detectors may be safely placed in the active state. the interval above also applies when the voltage multiplier is turned off (with power applied) via bits r 19 r 18 r 17 being 0 0 0. after the multiplier is turned back on, sufficient time must be allowed for the voltage to build on c mult . in this case, typically an external resistor does not allow the c mult voltage to discharge below approximately v pos (see section 5e, under c mult ) . note that if the voltage multiplier is not turned off (that is, the above bits are unequal to 0 0 0), the keepalive circuit maintains the multiplied voltage on c mult . ensuring valid counter programming before the plls and/or phase detectors are taken out of standby, legitimate divide ratios (pertinent to the application) must be loaded in the registers. for example, proper divide ratios must be loaded for the r, n, r , and n counters. also, proper values for all other bits must be loaded. for example: selection of crystal or external reference mode must be made prior to activation of the loops. after the ic is initialized with the proper bits loaded, the main loop may then be safely activated via the phase detector float bit and/or the pll standby bit being programmed to 0. allowing for overshoot the vco control voltage overshoot for the main loop must not be allowed to exceed the capability of the phase/ frequency detectors' maximum output voltage. the detectors' maximum output voltage is determined by the minimum voltage at c mult and the headroom required for the current source. see the following figure. steadystate control voltage vco control voltage voltage at c mult pin headroom for current source overshoot time for example, if the main supply voltage (v pos ) is 3 v and the voltage multiplier is utilized, the minimum voltage at c mult is 4.75 v. then, to allow for current source headroom, the maximum output voltage from the parameter table in section 3c is approximately c mult 0.6 v or 4.2 v approximately. thus, the maximum output overshoot voltage at the phase/frequency detector outputs should be no more than 4.2 v. continuing the above example, if the loop is designed with 20% overshoot in the vco control voltage, then the overshoot must be subtracted off of the 4.2 v shown above. therefore, the upper end of the control voltage to the vco must be no more than approximately 3.64 v. the equations below can be used to determine constraints: v f 1.2 2 a + 1 d v ssv max = v f a ( d v) 0.6 where d v is the vco control voltage range, the maximum minus the minimum voltage, v f is the minimum phase detector supply voltage (at the c mult pin) per the following table, a is the control voltage overshoot in decimal; for example, 20% overshoot is 0.2, and ssv max is the maximum allowed steadystate vco control voltage. minimum phase detector voltage from voltage multiplier supply voltage, v pos minimum phase detector voltage, v f 1.8 v 3.32 v 2.0 v 3.72 v 2.5 v 4.75 v 3.6 v 4.75 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 58 motorola rf/if device data enb d in clk bitgrabber access of the registers $0 accesses c register $1 accesses hr register $2 accesses n register $3 accesses d register $4 accesses hn register $5 accesses r register msb lsb 1234 8 clocks to access the c register 16 clocks to access the hr register 24 clocks to access the n register enb d in clk x lsb 123 4 32 clocks always used conventional access of the registers a0 a1 a2 a3 x x x 5678 9101112 32 address = when the pll device loads the data bit. 8. programmer's guide 8a. quick reference f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 59 motorola rf/if device data don't care nibble (shifted in first) least significant nibble (shifted in last) 0 c register conventional access 0 0 0 most significant nibble (shifted in first) out a out b/xref out c bitgrabber access pd float pd float pll stby pll stby osc stby least significant nibble (shifted in last) address nibble see below see below 8a. quick reference (continued) a3 a2 a1 a0 x xxx x xxx x xxx x xxx x xxx c7 c6 c5 c4 c3 c2 c1 c0 c7 c6 c5 c4 c3 c2 c1 c0 notes: 1. for the out a bit to control the output a pin as a port expander, bits r 21 r 20 must be 0 0, which selects output a as a generalpurpose output. if r 21 r 20 are not equal to 0 0, then the out a bit is a don't care. 2. whenever osc stby = 1, both pll stby and pll stby must be 1, also. out a = output a pin logic state 0 = pin is forced to 0 (power up default) 1 = pin is forced to 1 see note 1 out b/xref = output b pin logic state/ external reference selection see table below out c = output c pin logic state 0 = pin is forced to 0 (power up default) 1 = pin is forced to high impedance pd float = phase detector float 0 = active, normal operation (power up default) 1 = pd out hi/pd out lo are forced to high impedance pd float = phase detector float 0 = active, normal operation (power up default) 1 = pd out is forced to high impedance osc stby = oscillator standby 0 = active, normal operation (power up default) 1 = oscillator/reference circuit in standby see note 2 pll stby = pll standby 0 = active, normal operation 1 = main pll in standby (power up default) see table below pll stby = pll standby 0 = active, normal operation 1 = secondary pll in standby (power up default) mode pin and bit summary mode pin out b/xref bit pll stby bit reference circuit output b pin main pll 0 0 0 xtal osc mode 0 active 0 0 1 xtal osc mode z standby 0 1 0 xtal osc mode 1 active 0 1 1 xtal osc mode z standby 1 0 0 xtal osc mode 0 active 1 0 1 xtal osc mode z standby 1 1 0 external reference mode 1 active 1 1 1 external reference mode z standby notes: xtal osc = crystal oscillator. z = high impedance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 60 motorola rf/if device data hr register 8a. quick reference (continued) most significant nibble (shifted in first) msb of r counter divide value least significant nibble (shifted in last) lsb of r counter divide value example: to program the r counter to divide by 1000 in decimal, first multiply 1000 by 2 which is 2000. convert 2000 to hexadecimal: $7d0. then, add leading 0s to form 2 bytes (4 nibbles): $07d0. finally, load the hr register bits r15 to r0 with $07d0. when the n register is subsequently loaded, data passes from the first hr register (buffer) to the second r register (buffer). (data is still retained in the hr register.) with bitgrabber, no address bits are needed. with a conventional load, address bits a3 to a0 must be included. note: hexadecimal numbers are preceded with a dollar sign. for example: hexadecimal 1234 is shown as $1234. lsb of r counter divide value don't care nibble (shifted in first) least significant nibble (shifted in last) 0 conventional access 0 0 1 address nibble msb of r counter divide value bitgrabber access r7 . . . r4 r3 . . . r0 r11 . . . r8 r15 . . . r12 r7 . . . r4 r3 . . . r0 r15 . . . r12 r11 . . . r8 a3 a2 a1 a0 x xxx x xxx x xxx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 61 motorola rf/if device data don't care nibble (shifted in first) least significant nibble (shifted in last) 0 n register conventional access 0 1 0 most significant nibble (shifted in first) control ld window phase detector program msb of n counter divide value current ratio least significant nibble (shifted in last) 8a. quick reference (continued) address nibble control = control for auxiliary divider see table a ld window = lock detector window for main loop 0 = 32 osc e periods 1 = 128 osc e periods phase detector program = detector program for main loop see table b current ratio = pd out hi to pd out lo current ratio 0 = 4:1 1 = 8:1 lsb of n counter divide value example: to program the n counter to divide by 1000 in decimal, first convert to hexadecimal: $3e8. then, add leading 0s to form 2 leading bits plus 2 bytes (2 bits plus 4 nibbles); this is n17 to n0. bits n23 to n18 should be appropriate to control the above functions. finally, load the n register. loading the n register also causes data to pass from the hr register to the r register and data from the hn register to pass to the n register. with bitgrabber, no address bits are needed. with a conventional load, address bits a3 to a0 must be included. a3 a2 a1 a0 x x x x n23 . . . n20 n19 . . . n16 n15 . . . n12 n11 . . . n8 n7 . . . n4 n3 . . . n0 n3 . . . n0 n7 . . . n4 n11 . . . n8 n15 . . . n12 n19 n18 n17 n16 n23 n22 n21 n20 bitgrabber access see below table a. osc e to f out frequency ratio, mode = low n23 r 1 r 0 osc e to f out frequency ratio 0 0 0 10:1 0 0 1 12.5:1 0 1 0 12.5:1 0 1 1 12.5:1 1 0 0 8:1 1 0 1 10:1 1 1 0 10:1 1 1 1 10:1 note: when the mode pin is high, the f out pins are configured as polarity inputs and n23 must be programmed to 1. table b. main phase detector control n21 n20 n19 result 0 0 0 both pd out hi and pd out lo floating 0 0 1 pd out hi floating, pd out lo enabled 0 1 0 pd out hi enabled, pd out lo floating 0 1 1 both pd out hi and pd out lo enabled 1 0 0 pd out hi enabled and pd out lo floating for 16 f r cycles, then pd out hi floating and pd out lo enabled 1 0 1 pd out hi enabled and pd out lo floating for 32 f r cycles, then pd out hi floating and pd out lo enabled 1 1 0 pd out hi enabled and pd out lo floating for 64 f r cycles, then pd out hi floating and pd out lo enabled 1 1 1 pd out hi enabled and pd out lo floating for 128 f r cycles, then pd out hi floating and pd out lo enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 62 motorola rf/if device data don't care nibble (shifted in first) 0 r register 1 0 1 y coefficient output a function test/rst msb of r counter divide value vmult control least significant nibble (shifted in last) 8a. quick reference (continued) address nibble y coefficient 0 0 = only programming values allowed output a function = controls output a mux 0 0 = generalpurpose output 0 1 = f r 1 0 = f r 1 1 = phase detector pulse vmult control = voltage multiplier control 0 0 0 = multiplier off, 9 mhz osc e 80 mhz 0 0 1 = multiplier on, 9 mhz osc e 20 mhz 0 1 0 = multiplier on, 20 mhz < osc e 40 mhz 0 1 1 = multiplier on, 40 mhz < osc e 80 mhz test/rst = test/reset 0 = only programming value allowed lsb of r counter divide value example: when the mode pin is tied low, see table 21 for r counter programming. when the mode pin is tied high, to program the r counter to divide by 1000 in decimal, first multiply 1000 by 2, which is 2000. convert 2000 to hexadecimal: $7d0. then, add leading 0s to form 2 bytes (4 nibbles); this becomes bits r 15 to r 0. bits r 23 to r 16 should be appropriate to control the above functions. finally, load the r register. with a conventional load, address bits a3 to a0 must be included. note: hexadecimal numbers are preceded with a dollar sign. for example: hexadecimal 1234 is shown as $1234. r 23 r 22 r 21 r 20 r 19 r 18 r 17 r 16 r 15 . . . r 12 r 11 . . . r 8r 7 . . . r 4r 3 . . . r 0 a3 a2 a1 a0 x xxx conventional access only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 63 motorola rf/if device data a3 a2 a1 a0 don't care nibble (shifted in first) least significant nibble (shifted in last) 0 hn register 1 0 0 x xxx msb of n counter divide value 8a. quick reference (continued) n 15 . . . n 12 n 11 . . . n 8 n 7 . . . n 4 n 3 . . . n 0 address nibble example: to program the n counter to divide by 1000 in decimal, first multiply 1000 by 8, which is 8000. convert 8000 to hexadecimal: $1f40. then, add leading 0s (if necessary) to form 2 bytes (4 nibbles). finally, configure address bits a3 to a0 and load the hn register. when the n register is subsequently loaded, data passes from the first hn register (buffer) to the second n register (buffer). (data is still retained in the hn register.) x xxx x xxx lsb of n counter divide value conventional access only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 64 motorola rf/if device data a3 a2 a1 a0 don't care nibble (shifted in first) least significant nibble (shifted in last) 0 conventional access only 0 1 1 x xxx msb of dac2 8a. quick reference (continued) d15 . . . d12 d11 . . . d8 d7 . . . d4 d3 . . . d0 address nibble x xxx x xxx d register lsb of dac2 msb of dac1 lsb of dac1 dac2 value dac1 value dac2 value = analog output level of dac2 $00 = zero output $01 = zero + 1 lsb output $02 = zero + 2 lsbs output $03 = zero + 3 lsbs output ? ? ? $fd = full scale 2 lsbs output $fe = full scale 1 lsb output $ff = full scale output dac1 value = analog output level of dac1 $00 = zero output $01 = zero + 1 lsb output $02 = zero + 2 lsbs output $03 = zero + 3 lsbs output ? ? ? $fd = full scale 2 lsbs output $fe = full scale 1 lsb output $ff = full scale output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 65 motorola rf/if device data 8b. initializing the device introduction the registers retain data as long as power is applied to the device. the r and n registers contain counter divide ratios for the main loop, pll. the r and n registers contain counter divide ratios for the secondary loop, pll . additional control bits are located in the r , n, and c registers. the d register controls the dacs. section 8a is a handy reference for register access and bit definitions. the c, d, r , and n registers can be directly written, and have an immediate impact on chip operation. the hr and hn registers can be directly written, but have no immediate impact on chip operation. this is because the hr and hn registers are the frontends of double buffers. the hr register feeds the r register. the hn register feeds the n register. changing data in the r and/or n registers is done with a write to the hr and/or hn register, respectively, followed by a write to the n register. the transfer of data from the hr to r and hn to n registers is triggered with a write to the n register. typically, the hr and hn registers are written once, during initialization after power up. the hr and hn registers only need to be accessed if their data is changing. an example following is an initialization example for a system with a main loop that covers 450 to 500 mhz in 5 khz steps. an external reference of 19.44 mhz is utilized. the secondary loop is selected to run at 50 mhz. both vcos are positive polarity meaning that when the input control voltage increases, the output frequency increases. a divideddown reference is not needed (f out and f out ). therefore, the mode pin is tied to v pos and the pol and pol pins are tied to ground. the following initialization gives serial data examples for bitgrabber access of the c, hr, and n registers. initialization below is the sixstep initialization sequence used after power up for the example given above. programming the c register first is recommended if the voltage multiplier is utilized. there are three important criteria to note. violation of any criterion may cause the voltage multiplier to collapse. the first criterion is that after power up, a sufficient time interval must be provided (after the c and r registers are initialized) for the onchip voltage multiplier to build up the voltage on the c mult pin. this interval is determined by the external capacitor size tied to the c mult pin and the charging current which is about 100 m a. after this interval, the chip can maintain the voltage on the c mult pin and the phase/frequency detectors for the main loop may be safely activated. the second criterion is that before the phase/frequency detectors are activated, legitimate divide ratios (pertinent to the application) must be loaded in the registers. the third criterion is a hardware issue. the three criteria are discussed with more detail in section 7e. if the voltage multiplier is not used, step 1 is eliminated and the initialization sequence starts with step 2. step 1: load the c register the c register is programmed such that the main loop's phase/frequency detector outputs are floating (pd float bit c4 = 1), the reference circuit is active (osc stby bit c2 = 0), and an external reference is accommodated (out b/xref bit c6 = 1, with the mode pin high). when the voltage multiplier is enabled by programming the r register, the voltage is allowed to build on the c mult pin such that a voltage higher than the main supply voltage is providing power to the phase/frequency detectors. both loops are active (pll stby bits c1 = c0 = 0). also, for this example, output a and output c are programmed low (out bits c7 = c5 = 0). in summary, hexadecimal 58 or $58 is serially transferred (bitgrabber access with no address bits). step 2: load the r register for the secondary loop, the 19.44 mhz reference must be divided down to 80 khz by the r counter; the divide ratio is 243. per section 8a, the value is doubled to 486. the 16 lsbs of the r register determine the r counter divide ratio. therefore, 486 is converted to $01e6 and becomes the 16 lsbs (r 15 to r 0) in the r register. test/rst bit r 16 must be a 0. bits r 19 to r 17 determine the refresh rate of the voltage multiplier. the frequency at osc e is < 20 mhz. therefore, per section 8a, bits r 19 to r 17 must be 0 0 1. if output a is needed as a mcu port expander, bits r 21 = r 20 = 0. per section 8a, y coefficient bits r 23 = r 22 = 0. in summary, $050201e6 is serially transferred (conventional access with an address of 0 1 0 1). step 3: load the hr register for the main loop, the 19.44 mhz reference must be divided down to 5 khz by the r counter; the divide ratio is 3888. per section 8a, the ratio 3888 is doubled to 7776 and then converted to $1e60. the hr register value is programmed as $1e60. when the hr register contents are transferred to the r register, the r counter divide ratio is determined. in summary, $1e60 is serially transferred (bitgrabber access). this value is transferred from the hr to the r register when the n register is accessed in step 5. step 4: load the hn register for the secondary loop, the phase detector is chosen to run at 80 khz. therefore, 80 khz must be multiplied up to 50 mhz which is a factor of 625. per section 8a, the factor is first multiplied by 8 which equals 5000 and then converted to $1388. the hn register is programmed as $1388. when the hn register contents are transferred to the n register, the n counter divide ratio is determined. in summary, $04001388 is serially transferred (conventional access with an address of 0 1 0 0). the value $1388 is transferred to the n register when the n register is accessed in step 5. step 5: load the n register for this example, the ic is initialized to tune the lowest end of the main loop. the lowest end of the main loop's frequency range is 450 mhz. therefore, the 5 khz must be multiplied up to 450 mhz which is a factor of 90,000 or $15f90 to be loaded into bits n17 to n0 of the n register. bit n18 is programmed to 0 for a pd out hi to pd out lo current ratio of 4:1. if pd out lo is used for the main loop, bits n21 to n19 must be 0 0 1. (pd out lo must be used to initialize the device when adapt is used, see section 8d.) bit n22 = 0 to select a lock detect window of approximately 32 / osc e = 32 / 19.44 mhz or 1.6 m s. bit n23 must be programmed to 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 66 motorola rf/if device data by the user. (when the mode pin is high, programming n23 to a 0 is for motorola use only.) in summary, $895f90 is serially transferred (bitgrabber access). the n register access also causes doublebuffer transfers of hr to r and hn to n . step 6: load the c register now that legitimate divide ratios are programmed for the counters, the main loop may be activated. thus, the pd float bit c4 is now programmed to 0. the standby bits are unchanged: c2 = c1 = c0 = 0. bit c5 could be used to control output c to either a low level or high impedance; for a low level, c5 = 0. whenever an external reference is utilized, bit c6 must be 1. bit c7 may be used to control output a to a low or high level because it is selected as aport expandero by bit r 21 and r 20; for a low level, c7 = 0. in summary, $40 is serially transferred (bitgrabber access). this causes the main loop to tune to 450 mhz, the secondary loop to tune to 50 mhz, and both the output a and output c pins to be forced low. the device is now initialized. 8c. programming without adapt tuning the top of the band after initializing the device via steps 1 through 6 in section 8b, the only register that needs to be loaded to tune the main loop is the n register. for this example, tuning the upper end of the band (500 mhz) requires that the 5 khz at the phase/frequency detector be multiplied up to 500 mhz. this is a loop multiplying factor of 100,000. this value is converted to $186a0 and is loaded for bits n17 to n0. bits n23 to n18 are not changed and are programmed as indicated in section 8b, step 5. in summary, $8986a0 is transferred to tune the main loop. no other registers are loaded. tuning other channels tuning other channels for the main loop, while keeping the secondary loop at a constant frequency, only requires programming the n register. see table 22 for example frequencies. table 22. main loop tuning examples frequency desired (mhz) multiplying factor (decimal) multiplying factor (hexadecimal) n register data (hexadecimal) 450.000 90,000 $15f90 $895f90 450.005 90,001 $15f91 $895f91 450.010 90,002 $15f92 $895f92 450.015 90,003 $15f93 $895f93 455.000 91,000 $16378 $896378 458.015 91,603 $165d3 $8965d3 471.040 94,208 $17000 $897000 500.000 100,000 $186a0 $8986a0 8d. programming utilizing horseshoe with adapt introduction a unique adapt feature can be used with the MC145181 when conventional tuning can not meet the locktime requirements of a system and the annoying spurs or noise can not be tolerated from a fractionaln scheme. the adapt feature is available on the main loop only. for adapt, a timer is engaged which causes an internal data update of the r and n registers to be delayed. the ic supports the horseshoe scheme for adapt by allowing a fairlyclose quicklytuned approximate frequency to be tuned, followed by the tuning of the exact frequency. two sets of r and n data are sent to the device. the first set {r1, n1} is for tuning the approximate frequency. the second set {r2, n2} is for tuning the exact frequency. use of the timer delays the transfer of {r2, n2} until a programmed interval has elapsed. in addition, after the interval has elapsed, the main loop control switches from pd out hi to pd out lo. tuning near the top of the band continuing the example, after initializing the device via steps 1 through 6 in section 8b, horseshoe with adapt can be used to tune the main loop to obtain fast frequency jumps. use of the bitgrabber access is recommended to minimize the number of serial data clocks required for sending the four awordso. in this example, the first phase of adapt utilizes approximate tuning with the phase/frequency detector running at 4x the step size. therefore, the approximate tuning runs the detector at about 20 khz. the second phase, with exact tuning, runs the detector at 5 khz. horseshoe with adapt requires that two data sets be serially sent to the device for every frequency tuned. the first set is for approximate tuning {r1, n1}; the second set is for exact tuning {r2, n2}. approximate tuning with horseshoe is unique. this method involves two key elements: (1) increasing the phase detector frequency and (2) varying both the r and n divide values such that the approximate frequency is within a certain predetermined range. the horseshoe algorithm contained in the development system software also allows placing a constraint on the loopgain variation that the user can tolerate. for example, to tune 459.97 mhz, the first {r1, n1} data set could contain divide ratios for the r and n counters of 973.5 and 23,034, respectively. with this data set, the phase detector is running at about 19.97 khz and the approximate frequency is about 170 hz from the exact frequency. the second data set contains r and n divide values of 3,888 and 91,994, respectively. this achieves the exact (target) frequency of 459.97 mhz. the timer must be programmed to determine the interval that the device is in the approximatetune mode. for this example, assume this is 32 f r cycles; thus, bits n21 n20 n19 = 1 0 1 in the first data set. note that this time interval is 32 cycles of f r , with the phase detector running at about 20 khz (approximate tune) or about 1.6 ms plus the mcu shift time shown in figure 64. included in the first data set are n23 = 1 which is required when the mode pin is high, n22 = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 67 motorola rf/if device data for the lock detect window of 1.6 m s, and n18 = 0 for a current ratio of 4:1 (because the phase detector is running at approximately 4x the step size). note that bits n23, n22, and n18 are unchanged from the initialization values. for the second data set, bits n23, n22, and n18 are unchanged. bits n21, n20, and n19 must be programmed as 0 0 1. this enables pd out lo for the exact tune after time out. in summary, two data sets need to be sent to the device: {r1, n1} and {r2, n2}. they are sent in succession as r1, n1, r2, n2; where r1 is the r register value for the first data set, n1 is the n register value for the first set, etc. for the example, these values are {r1, n1} = {$079b, $a859fa} and {r2, n2} = {$1e60, $89675a}. see figure 64. tuning other channels tuning other channels for the main loop, while keeping the secondary loop at a constant frequency, requires sending two data sets to the part {r1, n1} and {r2, n2}. see table 23. 8e. controlling the dacs introduction the two 8bit dacs are independent circuit blocks on the chip. they have no interaction with other circuits on the chip. a single 16bit register, called the d register, holds the binary value which controls both dacs. programming the dacs a dac programmed for 0 scale is in the lowpower mode. the 0 scale is programmed as $00 for each 8bit dac. as an example, consider a system that uses just one of the dacs (dac 1). the other dac output is unused and is programmed for 0 output. if a condition for a system requires that the dac have a halfscale output, then dac 1 is programmed as $80. in summary, $03000080 is serially transferred (conventional access with an address of 0 0 1 1). table 23. main loop tuning using horseshoe with adapt desired approximate tuning exact tuning desired target frequency (mhz) r1 n1 frequency error (hz) r2 n2 450.000 $0798 $a857e4 0 $1e60 $895f90 450.005 $079b $a85807 548 $1e60 $895f91 450.020 $0798 $a857e5 0 $1e60 $895f94 450.255 $0795 $a857ce 162 $1e60 $895fc3 459.970 $079b $a859fa 170 $1e60 $89675a 500.000 $0798 $a861a8 0 $1e60 $8986a0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 68 motorola rf/if device data figure 64. figure 64. serial data format for horseshoe with adapt note: 224 1224 1224 12 16 12 16 1 exact tune total time out interval for approximate tune actual timer interval (do not shift in next channel) n2 r2 n1 r1 initialize n register after power up n21 n20 n19 001 101 n21 n20 n19 100 110 111 write hr register write n register enb high at least 20 osc cycles + 99 f cycles in write hr register write n register n21 n20 n19 001 internal data transfer of exact tune data, switch from pd hi to pd lo out out tune next channel, write hr register enb high at least 20 osc cycles enb high at least 20 osc cycles cock timer timer fires e e e enb clk d in (not drawn to scale) (not drawn to scale) the interval for shifting in exact tune {r2, n2} data adds to the actual approximate tuning time. however, this is usually insignificant. for example, at a data rate of 2 mbps (2 megabits per second), approximately 20 s is added to the approximate tuning time. m f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 69 motorola rf/if device data 9. application circuit figure 65. application circuit lowpass filter secondary vco lowpass filter optional 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 generalpurpose (opendrain) main vco generalpurpose (totempole) generalpurpose (threestate) note 4 dac power (note 3) reflex codec or mcu osc e dac v pos dac1 dac2 enb d in clk ld output b v pos f out /pol f out /pol v pos f in gnd osc b v pos pd out c reg c mult pd out lo pd out hi gnd rx output a output c gnd gnd f in f in v pos mode 12345678 24 23 22 21 20 19 18 17 v pos note 5 v pos 2 k v pos v pos MC145181 notes: 1. r should be chosen to achieve the desired isolation. use of a capacitor in place of r is possible, but there is the possibility of phase locking on vco harmonics if they fall on the highsensitivity point of the f in or f in input. this is because use of a capacitor in place of r forms a highpass filter. 2. v pos may range from 1.8 to 3.6 v. 3. dac power may be any potential between 1.8 v and 3.6 v. 4. configurable pins. see pin descriptions. 5. tie mode to gnd or v pos . r smd note 1 50 w smd 0.1 m f x7r 0805 smd or smaller r smd 50 w smd 0.1 m f x7r 0805 smd or smaller note 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 70 motorola rf/if device data 10. outline dimensions plastic package case 873c01 (lqfp32) issue a 6 h notes: 1. dimensions are in millimeters. and tolerancing per asme y14.5m, 1994. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datums a, b, and d to be determined where the leads exit the plastic body at datum plane h. 4. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. dambar can not be located on the lower radius or the foot. minimum space between a protrusion and an adjacent lead is 0.07 mm. 6. exact shape of corners may vary. dim min max millimeters a 1.60 a1 0.05 0.15 a2 1.35 1.45 b 0.18 0.27 b1 0.17 0.23 c 0.10 0.20 c1 0.09 0.16 d 7.00 bsc d1 5.00 bsc e 7.00 bsc e1 5.00 bsc e 0.50 bsc l 0.45 0.75 l1 1.00 ref r1 0.08 r2 0.08 0.20 s 0.20 0 7 0 11 13 11 13 1 2 3 e 2 d1 2 e 24 17 25 32 18 16 9 k seating d 2 e1 2 d a b c d d1 plane all 4 sides ab 0.10 d h e1 all 4 sides ab 0.20 d c j j 28x e 4x e/2 0.080 c a a2 a1 l1 l s 2 1 3 0.25 r2 r1 detail k ????? ????? ????? b1 b c1 c base metal plating ab m 0.08 d c section jj f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC145181 71 motorola rf/if device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : motorola japan ltd.; spd, strategic planning office, 141, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 4321 nishigotanda, shinagawaku, tokyo, japan. 81354878488 customer focus center: 18005216274 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, motorola fax back system us & canada only 18007741848 2, dai king street, tai po industrial estate, tai po, n.t., hong kong. http://sps.motorola.com/mfax/ 85226668334 home page : http://motorola.com/sps/ MC145181/d ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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